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5V551DCI

型号：

5V551DCI

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

4 页

PDF大小：

51 K

下载PDF手册
1:4 CLOCK BUFFER  
IDT5V551  
FEATURES:  
DESCRIPTION:  
• Advanced, low power CMOS process  
• 5V tolerant inputs  
The 5V551 clock driver is built using advanced CMOS technology. This  
lowskewclockdriveroffers1:4fanout. Thefanoutfromasingleinputreduces  
loading on the preceding driver and provides an efficient clock distribution  
network. The5V551offerslowcapacitanceinputs. Typicalapplicationsare  
clockandsignaldistribution.  
• Low skew outputs (<250ps)  
• Input/Output frequency up to 160MHz  
• Non-inverting output clock  
• Ideal for networking clocks  
• Operating voltage of 3V  
• Output enable mode tri-states outputs  
• Lead-free packaging available  
• Available in SOIC package  
PINCONFIGURATION  
FUNCTIONALBLOCKDIAGRAM  
Q1  
ICLK  
Q1  
1
2
OE  
8
7
VDD  
Q2  
Q3  
Q4  
Q2  
6
5
3
4
GND  
Q4  
ICLK  
Q3  
SOIC  
TOP VIEW  
OUTPUT ENABLE  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
MAY 2006  
1
c
2006 Integrated Device Technology, Inc.  
DSC - 6567/10  
IDT5V551  
1:4CLOCKBUFFER  
INDUSTRIALTEMPERATURERANGE  
ABSOLUTEMAXIMUMRATINGS(1)  
PINDESCRIPTION  
Symbol  
VDD  
Description  
Max.  
–0.5to+4.6  
–0.5to+7  
–0.5 to VDD + 0.5  
–40to+85  
–65to+150  
150  
Unit  
V
Name  
ICLK  
Qn  
Type  
Input  
Description  
ClockInput,internalpull-upresistor  
ClockOutputs  
SupplyVoltage  
VTERM  
AllInputs  
V
Output  
PWR  
PWR  
Input  
AllOutputs  
GND  
VDD  
ConnecttoGround  
TA  
TSTG  
TJ  
AmbientOperatingTemp  
StorageTemperature  
JunctionTemperature  
SolderingTemperature  
° C  
° C  
° C  
° C  
Connectto3.3V  
OE  
OutputEnable. Tri-statesoutputswhenLOW.  
Internalpull-upresistor.  
TSOLDER  
260  
NOTE:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
EXTERNALCOMPONENTS  
Aminimumnumberofexternalcomponentsarerequiredforproperoperation.  
Adecouplingcapacitorof0.01μFshouldbeconnectedbetweenVDD onpin7  
andGNDonpin6,asclosetothedeviceaspossible. A33Ωseriesterminating  
resistormaybeusedoneachclockoutputifthetraceislongerthanoneinch.  
RECOMMENDEDOPERATINGRANGE  
Symbol  
Description  
Min.  
–40  
3
Typ.  
—
Max.  
+85  
3.6  
Unit  
° C  
V
TA  
AmbientOperatingTemperature  
PowerSupplyVoltage (measuredinrespecttoGND)  
VDD  
—
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
FollowingConditionsApplyUnlessOtherwiseSpecified  
TA = -40°C to +85°C, VDD = 3.3V ± 5%  
Symbol  
VDD  
VIH  
Parameter  
Test Conditions  
Min.  
Typ.  
—
—
—
—
—
—
—
—
18  
Max.  
3.45  
—
Unit  
V
OperatingVoltage  
3.15  
(1)  
Input HIGH Voltage, ICLK  
VDD/2 + 0.7  
V
(1)  
VIL  
InputLOWVoltage,ICLK  
Input HIGH Voltage, OE  
Input LOW Voltage, OE  
OutputHIGHVoltage  
—
2
VDD/2 – 0.7  
—
V
VIH  
V
VIL  
—
0.8  
V
VOH  
VOL  
VOH  
IDD  
IOH = –25mA  
IOL = 25mA  
2.4  
—
V
OutputLOWVoltage  
—
0.4  
V
Output HIGH Voltage (CMOS)  
OperatingSupplyCurrent  
NominalOutputImpedance  
InternalPull-UpResistor  
InputCapacitance  
IOH = –12mA  
No Load, 135MHz  
VDD – 0.4  
—
—
V
—
mA  
Ω
ZO  
—
20  
—
RPU  
CIN  
ICLK, OE = 0V  
OE Pin  
—
350  
5
—
kΩ  
pF  
—
—
ICLK  
—
3
—
IOS  
ShortCircuitCurrent  
—
±90  
—
mA  
NOTE:  
1. Nominal switching threshold is VDD/2.  
2
IDT5V551  
1:4CLOCKBUFFER  
INDUSTRIALTEMPERATURERANGE  
ACELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
FollowingConditionsApplyUnlessOtherwiseSpecified  
TA = -40°C to +85°C, VDD = 3.3V ± 5%  
Symbol  
FIN  
Parameter  
Test Conditions  
Min.  
0
Typ.  
—
—
—
—
4
Max.  
160  
160  
1.5  
1.5  
8
Unit  
MHz  
MHz  
ns  
InputFrequency  
(1)  
FOUT  
tOR  
OutputFrequency  
15pFload  
—
—
—
2
OutputClockRiseTime  
0.8V to 2V  
tOF  
OutputClockFallTime  
2V to 0.8V  
ns  
(2)  
tPD  
PropagationDelay  
135MHz  
ns  
(3)  
tSK(O)  
OutputtoOutputSkew  
Risingedges atVDD/2  
—
—
250  
ps  
NOTES:  
1. With external series resistor of 33Ω positioned close to each output pin.  
2. With rail-to-rail input clock.  
3. Between any two outputs with equal loading.  
4. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.  
TESTCIRCUIT  
VDD  
VIN  
VOUT  
Pulse  
Generator  
D.U.T.  
RL  
CL  
RT  
TESTCONDITIONS  
Symbol  
VDD = 3.3V ± 5%  
Unit  
CL  
15  
pF  
Ω
Ω
ns  
RT  
ZOUT of pulse generator  
33  
RL  
tR/tF  
1 (0V to 3V or 3V to 0V)  
DEFINITIONS:  
CL = Load capacitance: includes jig and probe capacitance.  
RT = Termination resistance: should be equal to the ZOUT of the pulse generator.  
tR/tF = Rise/Fall time of the input stimulus from the pulse generator.  
3
IDT5V551  
1:4CLOCKBUFFER  
INDUSTRIALTEMPERATURERANGE  
ORDERINGINFORMATION  
XXXX  
X
X
Device Type  
Package Temp. Range  
I
Industrial (-40°C to +85°C)  
Small Outline IC  
SOIC - Green  
DC  
DCG  
5V551  
1:4 Clock Buffer  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
for Tech Support:  
clockhelp@idt.com  
www.idt.com  
4
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