IDT5T2010
INDUSTRIALTEMPERATURERANGE
2.5VZERODELAYPLLCLOCKDRIVER TERACLOCK
PINDESCRIPTION,CONTINUED
Symbol I/O
Type
Description
REF_SEL
I
LVTTL(1)
Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/
VREF1.
nsOE
I
LVTTL(1)
Synchronous output enable. When nsOE is HIGH, nQ[1:0] are synchronously stopped. OMODE selects
whether the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level
at which the outputs stop. When PE is LOW/HIGH, the nQ[1:0] is stopped in a HIGH/LOW state. When
OMODE is LOW, the outputs are tri-stated. Set nsOE LOW for normal operation.
QFB
QFB
O Adjustable(2) Feedback clock output
O Adjustable(2) Complementary feedback clock output
O Adjustable(2) Five banks of two outputs
nQ[1:0]
RxS
I
I
I
3-Level(3) Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF
clock input
TxS
3-Level(3) Sets the drive strength of the output drivers and feedback inputs to be 2.5V LVTTL (HIGH), 1.8V LVTTL
(MID) or HSTL/eHSTL (LOW) compatible. Used in conjuction with VDDQ to set the interface levels.
PE
LVTTL(1)
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive
edge of the reference clock (has internal pull-up).
nF[2:1]
FBF[2:1]
FS
I
I
I
I
I
LVTTL(1)
LVTTL(1)
LVTTL(1)
3-Level(3)
LVTTL(1)
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank (See Control Summary table)
Functionselectinputsfordivide-by-2,divide-by-4,zerodelay,orinvertonthefeedbackbank(SeeControlSummarytable)
Selects appropriate oscillator circuit based on anticipated frequency range. (See VCO Frequency Range Select.)
3-level inputs for feedback input divider selection (See Divide Selection table)
DS[1:0]
PLL_EN
PLL enable/disable control. Set LOW for normal operation. When PLL_EN is HIGH, the PLL is disabled and REF[1:0] goes
to all outputs.
PD
I
LVTTL(1)
Powerdowncontrol. WhenPDisLOW,theinputsaredisabledandinternalswitchingisstopped. OMODEselectswhether
the outputs are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop.
When PE is LOW/HIGH, the nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a LOW/HIGH
state. When OMODE is LOW, the outputs are tri-stated. Set PD HIGH for normal operation.
LOCK
O
I
LVTTL
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be
synchronizedtotheinputs. Theoutputwillbe2.5VLVTTL. (FormoreinformationonapplicationspecificuseoftheLOCK
pin, pleaseseeAN237.)
OMODE
LVTTL(1)
Outputdisablecontrol. Determinestheoutputs'disablestate. UsedinconjunctionwithnsOEandPD. (SeeOutputEnable/
Disable and Powerdown tables.)
NOTES:
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V
LVTTL signals as well.
VDDQ
PWR
Power supply for output buffers. When using 2.5V LVTTL, VDDQ should be connected to VDD.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
VDD
PWR
Power supply for phase locked loop, lock output, inputs, and other internal circuitry
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
OUTPUTENABLE/DISABLE
GND
PWR
Ground
nsOE
OMODE
Output
Normal Operation
Tri-State
VCOFREQUENCYRANGESELECT
L
H
H
X
L
H
FS(1)
LOW
HIGH
Min.
Max.
Unit
MHz
MHz
50
125
Gated(1)
100
250
NOTE:
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ[1:0] is stopped in a HIGH/LOW state.
1. The level to be set on FS is determined by the nominal operating frequency of the
VCO. The VCO frequency (FNOM) always appears at nQ[1:0] outputs when they are
operated in their undivided modes. The frequency appearing at the REF[1:0] and
REF[1:0] /VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and QFB
are undivided and DS[1:0] = MM. The frequency of REF[1:0] and REF[1:0] /VREF[1:0]
and FB and FB/VREF2 inputs will be FNOM/2 or FNOM/4 when the part is configured for
frequency multiplication by using a divided QFB and QFB and setting DS[1:0] = MM.
Using the DS[1:0] inputs allows a different method for frequency multiplication (see
Divide Selection table).
POWERDOWN
PD
OMODE
Output
Normal Operation
Tri-State
H
X
L
H
L
L
Gated(1)
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ[1:0] and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a
LOW/HIGH state.
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