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QST101AU6

型号：

QST101AU6

品牌：

STMICROELECTRONICS[ ST ]

页数：

30 页

PDF大小：

489 K

下载PDF手册
QST101  
Capacitive touch sensor device  
single key with individual key state output  
Preliminary Data  
Features  
■ Patented charge-transfer design  
■ Single QTouch™ key  
■ Individual key state output  
■ Fully “debounced” results  
VFQFPN8 (DFN8)  
■ Self-calibration and drift compensation  
■ Spread-spectrum bursts to reduce EMI  
■ Beeper output  
Description  
The QST101 is the ideal solution for the design of  
capacitive touch sensing user interfaces.  
■ Selectable Low Power mode  
■ Serial validation interface (SVI)  
Touch-sensitive controls are increasingly  
■ ECOPACK® (RoHS compliant) packages  
replacing electromechanical switches in home  
appliances, consumer and mobile electronics,  
and in computers and peripherals. Capacitive  
touch controls allow designers to create stylish,  
functional, and economical designs which are  
highly valued by consumers, often at lower cost  
than the electromechanical solutions they  
replace.  
Applications  
This device specifically targets human interfaces  
and front panels for a wide range of applications  
such as PC peripherals, home entertainment  
systems, gaming devices, lighting and appliance  
controls, remote controls, etc.  
The QST101 QTouch™ sensor IC is a pure digital  
solution based on Quantum's patented charge-  
transfer (QProx™) capacitive technology.  
QST devices are designed to replace mechanical  
switching/control devices and the reduced  
number of moving parts in the end product  
provides the following advantages:  
QTouch™ and QProx™ are trademarks of the  
Quantum Research Group.  
■ Lower customer service costs  
■ Reduced manufacturing costs  
■ Increased product lifetime  
Table 1.  
Device summary  
Feature  
QST101AU6  
Operating supply voltage  
Supported interface  
Operating temperature  
Package  
2.4V to 5.5V  
Individual key state output  
–40° to +85° C  
DFN8 (4.5 x 3.5 mm)  
April 2008  
Rev 1  
1/30  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
1
Contents  
QST101  
Contents  
1
2
3
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
QST touch sensing technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
3.1  
3.2  
3.3  
3.4  
3.5  
3.6  
3.7  
3.8  
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Spread-spectrum operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Detection threshold levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Detection integrator filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Self-calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Fast positive recalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Max on-duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Drift compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
4
Device operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
4.1  
4.2  
4.3  
4.4  
4.5  
4.6  
4.7  
4.8  
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Reset and power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
KOUT and KOUT outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Max on-duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Detection integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Serial validation interface (SVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
5
Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
5.1  
5.2  
CS sense capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Sensitivity tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
5.2.1  
5.2.2  
5.2.3  
Increasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Decreasing sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Key balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
5.3  
5.4  
5.5  
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Crosstalk precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
2/30  
QST101  
Contents  
5.6  
PCB layout and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
6.1  
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
6.1.1  
6.1.2  
6.1.3  
6.1.4  
6.1.5  
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
6.2  
6.3  
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
6.2.1  
6.2.2  
6.2.3  
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
6.3.1  
6.3.2  
6.3.3  
Functional EMS (electro magnetic susceptibility) . . . . . . . . . . . . . . . . . 18  
Electro magnetic interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 19  
6.4  
6.5  
6.6  
6.7  
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Capacitive sensing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
Output pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
6.7.1  
6.7.2  
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Output pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
6.8  
Serial validation interface (SVI) characteristics . . . . . . . . . . . . . . . . . . . . 24  
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25  
7.1  
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
8
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Device revision information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
9.1  
9.2  
Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Device revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
9.2.1  
Revision 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
10  
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
3/30  
Device overview  
QST101  
1
Device overview  
The QST101 capacitive touch sensor IC is a pure digital solution based on Quantum's  
patented charge-transfer (QProx™) capacitive technology.  
This technology allows users to create simple touch panel sensing electrode interfaces for  
conventional or flexible printed circuit boards (PCB/FPCB). Sensing electrodes are part of  
the PCB layout (copper pattern or printed conductive ink) and may be used in various  
shapes (circle, rectangular, etc.).  
By implementing the QProx™ charge-transfer algorithm, the QST101 detects finger  
presence (human touch) near electrodes behind a dielectric (glass, plastic, wood, etc.). Only  
one external sampling capacitor by channel is used in the measuring circuitry to control the  
detection.  
QST technology also incorporates advanced processing techniques such as drift  
compensation, auto-calibration, noise filtering, and Quantum's patented Adjacent Key  
Suppression™ (AKS™) to ensure maximum usability and control integrity.  
In order to meet environmental requirements, ST offers this device in ECOPACK®  
packages. These packages have a lead-free second level interconnect. The category of  
second level interconnect is marked on the package and on the inner box label, in  
compliance with JEDEC Standard JESD97.  
The maximum ratings related to soldering conditions are also marked on the inner box label.  
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.  
4/30  
QST101  
Pin description  
2
Pin description  
Figure 1.  
8-pin VFQFPN8 (DFN8) package pinout  
8
VSS  
1
VDD  
BEEPER/MOD  
KOUT/LP  
7
6
SNSK_SCK/SVI1  
SNS_SCK/SVI0  
2 (HS)  
QST101AU6  
3 (HS)  
(HS) 5  
KOUT/DI/SVI_DATA  
RESET/SVI_CLK  
4
(HS) 20 mA high sink capability (on N-buffer only)  
Table 2.  
Device pin description  
Type (1)  
Pin  
no.  
Pin name  
Function  
Supply voltage  
If unused  
1
2
VDD  
S
Beeper output (active low) and  
Max-On-Duration option resistor  
BEEPER/MOD (2)  
KOUT/LP (2)  
PP (HS)  
Option resistor  
Option resistor  
Key output (active low) and Low  
Power mode option resistor  
3
4
PP (HS)  
BD  
Reset pin (active low) and Serial  
Validation Interface clock output  
10nFcapacitor  
to ground  
RESET/SVI_CLK (3)  
Key output (active high), Detection  
Integrator option resistor and  
Serial Validation Interface data  
output  
5
6
KOUT/DI/SVI_DATA (2)  
SNS_SCK/SVI0  
PP (HS)  
SNS  
Option resistor  
Key sense pin to CS and Serial  
Validation Interface input 0  
Open  
Open  
Key sense pin to CS/RS and Serial  
Validation Interface input 1  
7
8
SNSK_SCK/SVI1  
VSS  
SNS  
S
Ground voltage  
1. S: supply pin, PP: Output push-pull pin, BD: bidirectional pin and SNS: Capacitive sensing pin  
2. During the reset phase, these pins are floating and their state depends on the option resistor.  
3. To ensure correct reset of device, a 10nF capacitor must be connected to this pin.  
5/30  
QST touch sensing technology  
QST101  
3
QST touch sensing technology  
3.1  
Functional description  
QST devices employ bursts of charge-transfer cycles to acquire signals. Burst mode permits  
low power operation, dramatically reduces RF emissions, lowers susceptibility to RF fields,  
and yet permits excellent speed. Signals are processed using algorithms pioneered by  
Quantum which are specifically designed to provide reliable, trouble-free operation over the  
life of the product.  
The QST switches and charge measurement hardware functions are all internal to the  
device. An external C capacitor accumulates the charge from sense-plate C , which is  
S
X
then measured. Larger values of C cause the charge transferred into C to rise more  
X
S
rapidly, reducing available resolution. As a minimum resolution is required for proper  
operation, this can result in dramatically reduced gain. Larger values of C reduce the rise  
S
of differential voltage across it, increasing available resolution by permitting longer QST  
bursts. The value of C can thus be increased to allow larger values of C to be tolerated.  
S
X
The device is responsive to both C and C , and changes in either can result in substantial  
X
S
changes in sensor gain.  
Figure 2. QTouch™ measuring circuitry  
CT (~5 pF)  
Sense resistor  
S (10 kΩ)  
R
Earth  
SNSK_SCKn  
SNS_SCKn  
Sense capacitor  
S (a few nF)  
C
Cx (~20 pF)  
Ai12569  
3.2  
Spread-spectrum operation  
The bursts operate over a spread of frequencies, so that external fields will have minimal  
effect on key operation and emissions are very weak. Spread-spectrum operation works  
with the Detection Integrator mechanism (DI) to dramatically reduce the probability of false  
detection due to noise.  
6/30  
QST101  
QST touch sensing technology  
3.3  
Detection threshold levels  
The key capacitance change induced by the presence of a finger is sensed by the variation  
in the number of charge transfer pulses to load the capacitor. The difference in the pulse  
count number is compared to a threshold in order to detect the key as pressed or not.  
Two different thresholds, one for detection and one for the end of detection, create an  
hysteresis in order to prevent erratic behavior.  
The default threshold levels and hysteresis values are described inSection 6.6: Capacitive  
sensing characteristics on page 20.  
3.4  
Detection integrator filter  
The Detection Integrator (DI) filter mechanism works together with spread spectrum  
operation to dramatically reduce the effects of noise on key states. The DI mechanism  
requires a specified number of measurements that qualify as detections (and these must  
occur in a row) or the detection will not be reported.  
In a similar manner, the end of a touch (loss of signal) also has to be confirmed over several  
measurements. It is called the End of Detection Integrator (EDI).  
This process acts as a type of “debounce” mechanism against noise.  
The default DI and EDI values for confirming start of touch and end of touch are described in  
Section 6.6: Capacitive sensing characteristics on page 20.  
Figure 3 shows an example of detection with DI=2 and EDI=2 meaning 3 consecutive  
samples are necessary to trigger the key detection or end of detection  
Figure 3.  
Detection signals  
Reference count  
Reference + EofDeTh  
Reference + DeTh  
Hysteresis  
Key Detection signal  
Time  
= Sampling point  
7/30  
QST touch sensing technology  
QST101  
3.5  
Self-calibration  
On power-up, all keys are self-calibrated to provide reliable operation under almost any  
conditions. The calibration phase is used to compute a reference value per key which is then  
used by the process determining if a key is touched or not. The reference is an average of 8  
single acquisitions. As a result, the calibration time of the system can be simply calculated  
using the following formula: t  
= 8 * Burst_Period. The methodology used to measure the  
CAL  
burst period is described in application note AN2547. For a maximum calibration duration  
(t ), please refer to Section 6.6: Capacitive sensing characteristics on page 20.  
CAL  
3.6  
3.7  
Fast positive recalibration  
The device autorecalibrates a key when its signal reflects a decrease in capacitance higher  
than a fixed threshold (PosRecalTh) for a defined number of acquisitions (PosRecalI).  
Max on-duration  
The device can time out and automatically recalibrate each key independently after a fixed  
duration of continuous touch detection. This prevents the keys from becoming ‘stuck on’ due  
to foreign objects or other sudden influences. This is known as the Max On-Duration feature.  
After recalibration, the key will continue to operate normally, even if partially or fully  
obstructed. Max On-Duration works independently per channel: a timeout on one channel  
has no effect on another channel.  
3.8  
Drift compensation  
Signal drift can occur because of changes in C , C , and V over time. Depending on the  
X
S
DD  
C type and quality, the signal may vary substantially with temperature and veiling. If keys  
S
are subject to extremes of temperature or humidity, the signal can also drift. It is crucial that  
drift be compensated, otherwise false detections, non detections, and sensitivity shifts will  
follow.  
Drift compensation slowly corrects the reference level of each key while no detection is in  
effect. The rate of reference adjustment must be performed slowly or else legitimate  
detections can also be ignored. The device compensates drift on each channel  
independently using a maximum compensation rate to the reference level.  
Once a touch is sensed, the drift compensation mechanism ceases since the signal is  
legitimately high, and therefore should not cause the reference level to change.  
The signal drift compensation is “asymmetric”: the reference level compensates drift in one  
direction faster than it does in the other. Specifically, it compensates faster for increasing  
signals than for decreasing signals. Decreasing signals should not be compensated for  
quickly, since an approaching finger could be compensated for partially or entirely while  
approaching the sense electrode. However, an obstruction over the sense pad, for which the  
sensor has already made full allowance, could suddenly be removed leaving the sensor with  
an artificially elevated reference level and thus become insensitive to touch. In this latter  
case, the sensor will compensate for the object's removal very quickly, usually in only a few  
seconds.  
8/30  
QST101  
QST touch sensing technology  
Figure 4 illustrates an example of the drift compensation algorithm following a temperature  
change.  
Figure 4.  
Drift compensation example  
Reference Count + PosRelTh  
Reference Count  
Temperature Change  
Reference + DeTh  
Drift Compensation  
Time  
9/30  
Device operating mode  
QST101  
4
Device operating mode  
4.1  
Main features  
●
●
●
●
●
●
●
Pins KOUT (active high) and KOUT (active low) directly reflect the state of the key  
Beeper output  
Selectable sleep duration (Low power mode)  
Selectable Max On-Duration  
Selectable Detection Integrator  
Selectable Low Power mode  
Serial validation interface (SVI)  
Figure 5.  
QST101 schematic diagram  
VDD  
2.4~5.5V  
Volt. Reg.  
VUNREG  
100nF  
4.7µF  
4.7µF  
1
Keep these parts close to IC  
V
DD  
10kΩ  
7
Key  
SNSK_SCK/SVI1  
SNS_SCK/SVI0  
C
S
R
SVI  
6
10kΩ  
5 (HS)  
KOUT/DI/SVI_DATA  
KOUT  
VDD  
VSS  
1MΩ  
3 (HS)  
2 (HS)  
KOUT/LP  
KOUT  
VDD  
1MΩ  
1MΩ  
4
VSS  
RESET/SVI_CLK  
10nF  
BEEPER/MOD  
BEEPER  
VDD  
VSS  
V
SS  
8
Ai12580  
4.2  
Reset and power-up  
At power-up, the device configures itself according to the pull-up or pull-down option  
resistors present on pins MOD, LP, DI. The device start-up and configuration may take up to  
t
.
Setup  
When the power is established, it is possible to force a new device configuration by applying  
a negative pulse on the RESET pin.  
The RESET pin is a bidirectional pin with an internal pull-up. The line is forced low when the  
device resets itself.  
A 10nF capacitor is recommended on the RESET pin to ensure reliable start-up and noise  
immunity.  
10/30  
 
QST101  
Device operating mode  
4.3  
KOUT and KOUT outputs  
Output pins KOUT (active high) and KOUT (active low) directly reflect the state of the key.  
These pins are push-pull outputs.  
During QST device reset phase, these pins are floating and their state depends on the  
option resistors.  
Pin KOUT is active high, meaning when the key is “touched”, the pin outputs a ‘1’.  
Pin KOUT is active low, meaning when the key is “touched”, the pin outputs a ‘0’.  
4.4  
4.5  
Beeper  
The beeper output may be used to drive a piezo-electric beeper to emit a sound on a key  
change.  
Each key change triggers on this pin the generation of a low pulse having a 90ms duration.  
Low power mode  
Low power mode is enabled using the LP option resistor as described in Table 3.  
If Low Power mode is selected, a 100ms window with very low power consumption is  
inserted after each acquisition.  
If a change is detected on a key, in order to speed up the DI process, the sleep window  
insertion is skipped until the end of the DI process.  
Table 3.  
Low power mode truth table  
LP pin  
Description  
VSS  
VDD  
Disabled  
Low Power mode is enabled (100ms sleep duration)  
4.6  
Max on-duration  
The Max On-Duration feature is enabled using the MOD option resistor. When the MOD  
option resistor is connected to V , the MOD time is set to 10 seconds. This means that a  
DD  
continuous "touched" detection for 10 seconds on the key triggers a recalibration.  
Table 4.  
Max On-Duration (MOD) truth table  
MOD pin  
Description  
VSS  
VDD  
Infinite  
10 seconds  
11/30  
Device operating mode  
QST101  
4.7  
Detection integrator  
The Detection Integrator values are configurable using the DI option resistor.  
Table 5.  
Detection Integrator (DI) truth table  
DI pin  
Description  
VSS  
VDD  
2 acquisitions  
6 acquisitions  
4.8  
Serial validation interface (SVI)  
The serial validation interface (SVI) acts as an SPI master device. It provides access to the  
following internal device information:  
●
device identifier string sent once after the Reset phase  
internal system parameters sent after each acquisition  
●
–
–
–
key state  
key reference  
key signal  
This data access facilitates system tuning and can be used as a debug interface.  
In SVI mode, the device operates normally with SVI data and clock signals being output on  
pins KOUT and RESET, respectively.  
To enter SVI mode, before power-up connect resistor R  
between SVI input 0 and SVI  
SVI  
input 1 pins as shown in Figure 5. Then, within 10 seconds following power-up disconnect  
resistor R in order to not modify Key electrode calibration and operation.  
SVI  
After the 10 seconds entering SVI sequence, and before the device resumes normal  
operation, the first data sent through the SVI is the “Device String Identifier”.  
Table 6.  
Device string identifier  
ASCII  
ASCII  
Char3  
ASCII  
Char4  
ASCII  
Char5  
ASCII  
Char6  
ASCII  
Char7  
Hex Char0 Hex Char1  
Char2  
1
0
“Q”  
“S”  
“T”  
“1”  
“0”  
“1”  
During normal operation, the device outputs the internal parameters after every key  
acquisition.  
Table 7.  
Byte No.  
Device internal parameters  
Bit 7 Bit 6 Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0
1
2
3
4
Key State  
Key MSB Reference  
Key LSB Reference  
Key MSB Signal  
Key LSB Signal  
Please refer to RM0014: QST serial validation interface reference manual for more  
information about the SVI operating mode.  
12/30  
QST101  
Design guidelines  
5
Design guidelines  
5.1  
CS sense capacitor  
The C sense capacitors accumulate the charge from the key electrodes and determine  
S
sensitivity. Higher values of C make the corresponding sensing channel more sensitive.  
S
The values of C can differ for each channel, permitting differences in sensitivity from key to  
S
key or to balance unequal sensitivities. Unequal sensitivities can occur due to key size and  
placement differences and stray wiring capacitances. More stray capacitance on a sense  
trace will desensitize the corresponding key. Increasing the C for that key will compensate  
S
for the loss of sensitivity.  
The C capacitors can be virtually any plastic film or low- to medium-K ceramic capacitor.  
S
The normal C range is 1nF to 50nF depending on the sensitivity required: larger values of  
S
C require better quality to ensure reliable sensing. In certain circumstances the normal C  
range may be exceeded. Acceptable capacitor types for most uses include PPS film,  
S
S
polypropylene film, and NP0 and X5R / X7R ceramics. Lower grades than X5R or X7R are  
not recommended.  
5.2  
Sensitivity tuning  
Sensitivity can be altered to suit various applications and situations on a channel-by-  
channel basis. The easiest and most direct way to impact sensitivity is to alter the value of  
each C : more C yields higher sensitivity. Each channel has its own C value and can  
S
S
S
therefore be independently adjusted.  
5.2.1  
5.2.2  
Increasing sensitivity  
Sensitivity can also be increased by using larger electrode areas, reducing panel thickness,  
or using a panel material with a higher dielectric constant.  
Decreasing sensitivity  
In some cases the circuit may be too sensitive. Gain can be lowered further by a number of  
strategies:  
●
●
●
making the electrode smaller  
making the electrode into a sparse mesh using a high space-to-conductor ratio  
decreasing the C capacitors  
S
5.2.3  
Key balance  
A number of factors can cause sensitivity imbalances. Notably, SNS wiring to electrodes can  
have differing stray amounts of capacitance to ground. Increasing load capacitance will  
cause a decrease in gain. Key size differences, and proximity to other metal surfaces can  
also impact gain.  
The keys may thus require “balancing” to achieve similar sensitivity levels. This can be best  
accomplished by trimming the values of the C capacitors to achieve equilibrium. The R  
S
S
resistors have no effect on sensitivity and should not be altered. Load capacitances to  
ground can also be added to overly sensitive channels to reduce their gain.  
These should be in the order of a few picofarads.  
13/30  
Design guidelines  
QST101  
5.3  
Power supply  
If the power supply fluctuates slowly with temperature, the QST device compensates  
automatically for these changes with only minor changes in sensitivity. However, if the  
supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep  
up, causing sensitivity anomalies or false detections.  
The power supply should be locally regulated, using a three-terminal regulator. If the supply  
is shared with another electronic system, care should be taken to ensure that the supply is  
free of digital spikes, sags and surges which can cause adverse effects. It is not  
recommended to include a series inductor in the power supply to the QST device.  
For proper operation, a 0.1 µF or greater bypass capacitor must be used between V and  
DD  
V
V
. The bypass capacitor should be routed with very short tracks to the device’s V and  
pins.  
SS  
SS  
DD  
The PCB should, if possible, include a copper pour under and around the device, but not  
extensively under the SNS lines.  
5.4  
5.5  
ESD protection  
In normal environmental conditions, only one series resistor is required for ESD  
suppression. A 10 kOhm R resistor in series with the sense trace is sufficient in most  
cases. The dielectric panel (glass or plastic) usually provides a high degree of isolation to  
prevent ESD discharge from reaching the circuit. R should be placed close to the chip. If  
S
S
the C load is high, R can prevent total charge and transfer and as a result gain can  
X
S
deteriorate. If a reduction in R increases gain noticeably, the lower value should be used.  
Conversely, increasing the R can result in added ESD and EMC benefits, provided that the  
increase does not decrease sensitivity.  
S
S
Crosstalk precautions  
Adjacent sense traces might require intervening ground traces in order to reduce capacitive  
cross bleed if high sensitivity is required or high values of delta-C are anticipated (for  
X
example, from direct human touch to an electrode connection). In normal touch applications  
behind plastic panels, this is rarely a problem regardless of how the electrodes are wired.  
Higher values of R will make crosstalk problems worse; try to keep R to 22 kOhm or less  
S
S
if possible. In general try to keep the QST device close to the electrodes and reduce the  
adjacency of the sense wiring to ground planes and other signal traces; this will reduce the  
C load, reduce interference effects, and increase signal gain. The one and only valid  
x
reason to run ground near SNS traces is to provide crosstalk isolation between traces, and  
then only on an as-needed basis.  
5.6  
PCB layout and construction  
The PCB traces, wiring, and any components associated with or in contact with either SNS  
pin will become touch sensitive and should be treated with caution to limit the touch area to  
the desired location.  
Multiple touch electrodes connected to any sensing channel can be used, for example, to  
create control surfaces on both sides of an object.  
14/30  
QST101  
Design guidelines  
It is important to limit the amount of stray capacitance on the SNS terminals, for example by  
minimizing trace lengths and widths to allow for higher gain without requiring higher values  
of C . Under heavy delta-C loading of one key, cross coupling to another key’s trace can  
S
X
cause the other key to trigger. Therefore, electrode traces from adjacent keys should not be  
run close to each other over long runs in order to minimize cross-coupling if large values of  
delta-C are expected, for example when an electrode is directly touched. This is not a  
X
problem when the electrodes are working through a plastic panel with normal touch  
sensitivity.  
For additional information on PCB layout and construction, please contact your local ST  
Sales Office for a list of available application notes.  
15/30  
Electrical characteristics  
QST101  
6
Electrical characteristics  
6.1  
Parameter conditions  
Unless otherwise specified, all voltages are referred to V  
.
SS  
6.1.1  
Minimum and maximum values  
Unless otherwise specified the minimum and maximum values are guaranteed in the worst  
conditions of ambient temperature, supply voltage and frequencies by tests in production on  
100% of the devices with an ambient temperature at T = 25°C and T = T max (given by  
A
A
A
the selected temperature range).  
Data based on characterization results, design simulation and/or technology characteristics  
are indicated in the table footnotes and are not tested in production. Based on  
characterization, the minimum and maximum values refer to sample tests and represent the  
mean value plus or minus three times the standard deviation (mean 3Σ).  
6.1.2  
Typical values  
Unless otherwise specified, typical data are based on T = 25 °C, V = 5 V (for the 4.5V ≤  
A
DD  
V
≤ 5.5 V voltage range) and V = 3.3 V (for the 3.0 V ≤ V ≤ 3.6 V voltage range).  
DD  
DD DD  
They are given only as design guidelines and are not tested.  
6.1.3  
6.1.4  
Typical curves  
Unless otherwise specified, all typical curves are given only as design guidelines and are  
not tested.  
Loading capacitor  
The loading conditions used for pin parameter measurement are shown in Figure 6.  
Figure 6.  
Pin loading conditions  
Output pin  
16/30  
QST101  
Electrical characteristics  
6.1.5  
Pin input voltage  
The input voltage measurement on a pin of the device is described in Figure 7.  
Figure 7. Pin input voltage  
Input pin  
VIN  
6.2  
Absolute maximum ratings  
Stresses above those listed as “absolute maximum ratings” may cause permanent damage  
to the device. This is a stress rating only and functional operation of the device under these  
conditions is not implied. Exposure to maximum rating conditions for extended periods may  
affect device reliability.  
6.2.1  
Thermal characteristics  
Table 8.  
Symbol  
Thermal characteristics  
Ratings  
Value  
Unit  
TSTG  
TJ  
Storage temperature range  
−65 to +150  
°C  
Maximum junction temperature (1)  
150  
1. The maximum chip-junction temperature is based on technology characteristics.  
6.2.2  
Voltage characteristics  
Table 9.  
Symbol  
Voltage characteristics  
Ratings  
Maximum value  
Unit  
VDD − VSS Supply voltage  
VIN  
Input voltage on any pin (1)(2)  
7.0  
V
VSS−0.3 to VDD+0.3  
1. Directly connecting output and RESET pins to VDD or VSS could damage the device if an unintentional  
internal reset is generated.  
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum  
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive  
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS  
.
17/30  
Electrical characteristics  
QST101  
6.2.3  
Current characteristics  
Table 10. Current characteristics  
Symbol  
Ratings  
Maximum value Unit  
IVDD  
IVSS  
Total current into VDD power lines (source)(1)  
Total current out of VSS ground lines (sink)(1)  
Output current sunk by output pins  
75  
150  
20  
IIO  
mA  
Output current source by output pins  
− 25  
(2)(3)  
IINJ(PIN)  
Injected current on output pins  
5
(2)  
ΣIINJ(PIN)  
Total injected current (sum of all I/O and control pins)  
20  
1. All power (VDD) and ground (VSS) lines must always be connected to the external supply.  
2. IINJ(PIN) must never be exceeded. This is implicitly ensured if VIN maximum is respected. If VIN maximum  
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive  
injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS  
.
3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the  
positive and negative injected currents (instantaneous values).  
6.3  
EMC characteristics  
Susceptibility tests are performed on a sample basis during product characterization.  
6.3.1  
Functional EMS (electro magnetic susceptibility)  
The product is stressed by two electro magnetic events until a failure occurs:  
●
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the  
device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2  
standard.  
●
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V and  
DD  
V
through a 100pF capacitor, until a functional disturbance occurs. This test  
SS  
conforms with the IEC 1000-4-4 standard.  
A device reset allows normal operations to be resumed. The test results are given in the  
table below based on the EMS levels and classes defined in application note AN1709.  
Table 11. Functional EMS  
Level/  
Class  
Symbol  
Parameter  
Conditions  
Voltage limits to be applied on any I/O  
pin to induce a functional disturbance  
VDD=5V, TA=+25°C,  
VFESD  
3B  
4A  
complies with IEC 1000-4-2  
Fast transient voltage burst limits to be  
applied through 100pF on VDD and VDD  
pins to induce a functional disturbance  
VDD=5V, TA=+25°C  
complies with IEC 1000-4-4  
VFFTB  
18/30  
QST101  
Electrical characteristics  
6.3.2  
Electro magnetic interference (EMI)  
The product is monitored in terms of emission. This emission test is in line with the norm  
SAE J 1752/3 which specifies the board and the loading of each pin.  
Table 12. EM emissions  
Monitored  
Symbol Parameter  
Conditions  
f
DEVICE = 4 MHz (1) Unit  
Frequency Band  
0.1 MHz to 30 MHz  
30 MHz to 130 MHz  
130 MHz to 1 GHz  
SAE EMI Level  
20  
VDD=5V, TA=+25°C,  
complies with SAE J  
1752/3  
20  
13  
dBμV  
SEMI  
Peak level  
2.5  
-
1. Data based on characterization results, not tested in production.  
6.3.3  
Absolute maximum ratings (electrical sensitivity)  
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the  
product is stressed in order to determine its performance in terms of electrical sensitivity.  
For more details, refer to the application note AN1181.  
Electro-static discharge (ESD)  
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are  
applied to the pins of each sample according to each pin combination. The sample size  
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models  
can be simulated: Human Body Model and Charge Device Model. These tests comply with  
JESD22-A114A/A115A specifications.  
Table 13. Absolute maximum ratings  
Symbol  
Ratings  
Conditions  
TA=+25°C  
TA=+25°C  
Maximum value (1) Unit  
Electro-static discharge voltage  
(Human Body Model)  
VESD(HBM)  
4000  
500  
V
V
Electro-static discharge voltage  
(Charge Device Model)  
VESD(CDM)  
1. Data based on characterization results, not tested in production.  
Static and dynamic latch-up  
●
LU: 3 complementary static tests are required on 10 parts to assess the latch-up  
performance. A supply overvoltage (applied to each power supply pin) and a current  
injection (applied to each input, output and configurable I/O pin) are performed on each  
sample. This test conforms to the EIA/JESD 78 IC latch-up standard.  
●
DLU: Electro-Static Discharges (one positive then one negative test) are applied to  
each pin of 3 samples when the micro is running to assess the latch-up performance in  
dynamic mode. Power supplies are set to the typical values, the oscillator is connected  
as near as possible to the pins of the micro and the component is put in reset mode.  
This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards.  
For more details, refer to the application note AN1181.  
19/30  
Electrical characteristics  
QST101  
Class (1)  
Table 14. Electrical sensitivities  
Symbol  
Parameter  
Conditions  
LU  
Static latch-up class  
TA=+125°C  
VDD=5.5V, fDEVICE = 4MHz, TA=+25°C  
A
A
DLU  
Dynamic latch-up class  
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the  
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B  
Class strictly covers all the JEDEC criteria (international standard).  
6.4  
6.5  
Operating conditions  
Table 15. Operating conditions  
Symbol  
Paremeter  
Conditions  
Min.  
Max.  
Unit  
VDD  
TA  
Operating supply voltage  
Operating temperature  
fDEVICE = 4 MHz  
2.4  
5.5  
V
–40  
+85  
°C  
Supply current characteristics  
(1)  
Table 16. Supply current characteristics  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Unit  
VDD = 2.4 V  
1.50  
1.95  
2.95  
135  
200  
300  
Average suppy current  
when one key is  
“touched”  
V
DD = 3.3 V  
DD = 5 V  
mA  
µA  
V
IDD  
VDD = 2.4 V  
Average suppy current  
when no key is “touched”  
V
DD = 3.3 V  
DD = 5 V  
V
1. The results are performed at T = 25°C and based on CS = 2.7nF.  
6.6  
Capacitive sensing characteristics  
Table 17. External sensing components  
Symbol  
Parameter  
Min.  
Typ.  
Max.  
Unit  
CS  
CX  
CT  
RS  
Sense capacitor  
100  
100  
nF  
pF  
Equivalent electrode capacitor  
Equivalent touch capacitor  
Serial resistance  
5
pF  
10  
22  
kOhm  
20/30  
QST101  
Electrical characteristics  
Table 18. Capacitive sensing parameters  
Symbol  
Parameter  
Calibration duration  
Min.  
Default  
Max.  
Unit  
tCAL  
tSetup  
ms  
ms  
Setup duration  
100  
DI  
Detection integrator  
Counts  
Counts  
Counts  
Counts  
Counts  
Counts  
s
See Note 1  
DeTh  
Detection threshold  
-10  
EDI  
End of detection integrator  
End of detection threshold  
Positive recalibration integrator  
2
EofDeTh  
PosRecalI  
-6  
10  
PosRecalTh Positive recalibration threshold  
MaxOnDuration Max on-duration  
6
See Note 1  
PosDiffDrift  
NegDiffDrift  
Positive differential drift compensation rate  
s/level  
s/level  
0.3  
1
Negative differential drift compensation rate  
PosDriftI  
NegDriftI  
DiffFact  
Positive drift integrator  
Negative drift integrator  
Differential time step factor  
Burst length  
3
10  
10  
BurstCount  
20  
2000 Counts  
Note:  
1
Please refer to Section 4: Device operating mode for option configuration and parameter  
values.  
6.7  
Output pin characteristics  
6.7.1  
General characteristics  
Subject to general operating conditions for V and T unless otherwise specified.  
DD  
A
Table 19. General characteristics  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Unit  
IL  
Input leakage current  
Output pin capacitance  
VSS ≤ VIN ≤ VDD  
1
μA  
COUT  
5
pF  
CL = 50 pF  
Between 10%  
and 90%  
tfOut  
trOut  
Output high to low level fall time  
Output low to high level rise time  
25  
25  
ns  
21/30  
Electrical characteristics  
QST101  
6.7.2  
Output pin characteristics  
Subject to general operating conditions for V and T unless otherwise specified.  
DD  
A
Table 20. Output pin current (V = 2.4V)  
DD  
Symbol  
Parameter  
Conditions  
Min.  
Max.  
Unit  
(1)  
VOL  
Output low level voltage for output pins  
Output high level voltage for output pins  
IIO = +8mA  
IIO = -2mA  
0.6  
V
(1)  
VOH  
VDD−0.9  
1. Not tested in production, based on characterization results.  
Table 21. Output pin current (V = 3.3V)  
DD  
Symbol  
Parameter  
Conditions  
Min.  
Max.  
Unit  
(1)  
VOL  
Output low level voltage for output pins  
Output high level voltage for output pins  
IIO = +8mA  
IIO = -2mA  
0.5  
V
(1)  
VOH  
VDD−0.8  
1. Not tested in production, based on characterization results.  
Table 22. Output pin current (V = 5V)  
DD  
Symbol  
Parameter  
Conditions  
Min.  
Max.  
Unit  
IIO = +20mA  
IIO = +8mA  
IIO = -5mA  
IIO = -2mA  
1.3  
(1)  
VOL  
Output low level voltage for output pins  
0.75  
V
VDD−1.5  
VDD−0.8  
(2)  
VOH  
Output high level voltage for output pins  
1. The output pin current sunk must always respect the absolute maximum rating specified in Table 10 and  
the sum of output pins must not exceed IVSS  
.
2. The output pin current sourced must always respect the absolute maximum rating specified in Table 10  
and the sum of output pins must not exceed IVDD  
.
Figure 8.  
Typical V at V = 2.4V  
Figure 9.  
Typical V at V = 3V  
OL DD  
OL  
DD  
1200  
1000  
800  
600  
400  
200  
0
1400  
1200  
1000  
800  
600  
400  
200  
0
-45°C  
25°C  
-45°C  
25°C  
90°C  
130°C  
90°C  
130°C  
0
2
4
6
8
10  
12  
14  
16  
0
2
4
6
8
10  
12  
14  
16  
18  
20  
Iol [mA]  
Iol [mA]  
Figure 10. Typical V -V at V = 3V  
Figure 11. Typical V at V = 5V  
OL DD  
DD OH  
DD  
1800  
1600  
1400  
1200  
1000  
800  
800  
700  
600  
500  
400  
300  
200  
100  
0
-45°C  
25°C  
90°C  
-45°C  
25°C  
90°C  
130°C  
130°C  
600  
400  
200  
0
0
2
4
6
8
10  
12  
14  
16  
18  
Iol [mA]  
0
2
4
6
8
10  
Iol [mA]  
12  
14  
16  
18  
20  
22/30  
QST101  
Electrical characteristics  
Figure 12. Typical V -V at V = 2.4V  
Figure 13. Typical V -V at V = 5V  
DD OH DD  
DD OH  
DD  
1800  
1600  
1400  
1200  
1000  
800  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
-45°C  
25°C  
90°C  
-45°C  
25°C  
90°C  
130°C  
130°C  
600  
400  
200  
0
0
2
4
6
8
10  
Iol [mA]  
12  
14  
16  
18  
20  
0
2
4
6
8
10  
12  
Iol [mA]  
Figure 14. Typical V vs. V  
OL  
DD  
100  
90  
80  
70  
60  
50  
40  
500  
450  
400  
350  
300  
250  
200  
150  
100  
-45°C  
-45°C  
25°C  
25°C  
90°C  
130°C  
90°C  
130°C  
2.4 2.6 2.8  
3
3.2 3.4 3.6 3.8  
4
4.2 4.4 4.6 4.8  
Vdd [V]  
5
5.2 5.4 5.6 5.8  
6
2.4 2.6 2.8  
3
3.2 3.4 3.6 3.8  
4
4.2 4.4 4.6 4.8  
Vdd [V]  
5
5.2 5.4 5.6 5.8  
6
900  
800  
700  
600  
500  
400  
300  
200  
-45°C  
25°C  
90°C  
130°C  
2.4 2.6 2.8  
3
3.2 3.4 3.6 3.8  
4
4.2 4.4 4.6 4.8  
5
5.2 5.4 5.6 5.8  
6
Vdd [V]  
Figure 15. Typical V -V vs. V  
DD OH  
DD  
200  
180  
160  
140  
120  
100  
80  
700  
600  
500  
400  
300  
200  
100  
-45°C  
-45°C  
25°C  
25°C  
90°C  
130°C  
90°C  
130°C  
60  
40  
2.4 2.6 2.8  
3
3.2 3.4 3.6 3.8  
4
4.2 4.4 4.6 4.8  
Vdd [V]  
5
5.2 5.4 5.6 5.8  
6
2.4 2.6 2.8  
3
3.2 3.4 3.6 3.8  
4
4.2 4.4 4.6 4.8  
Vdd [V]  
5
5.2 5.4 5.6 5.8  
6
23/30  
Electrical characteristics  
QST101  
6.8  
Serial validation interface (SVI) characteristics  
Table 23. SVI timing characteristics  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Unit  
f
SVI Clock frequency  
111  
33  
133  
kHz  
%
SVI  
ClkDtyC Clock Duty cycle  
tCTED  
tDTC  
tIB  
Time from Clock to End of Data  
5.56  
1.6  
6.96  
2
µs  
µs  
µs  
Time from Data to Clock  
Inter Byte Timing  
13.36  
16.7  
Low Power  
Mode Off  
2.85  
3.57  
tIF  
Inter Frame Timing  
ms  
Low Power  
Mode On  
2.85+tsleep 3.57+tsleep  
Figure 16. SVI clock and data timing  
Data bit  
Clock Pulse  
f
SVI  
tCTED  
tDTC  
Figure 17. SVI byte and frame timing  
Byte n  
Byte n+1  
tIB  
Frame n  
Frame n+1  
tIF  
24/30  
QST101  
Package mechanical data  
7
Package mechanical data  
Figure 18. 8-pin, very thin, fine pitch, quad flat package (DFN) outline  
Bottom View  
D
D2  
Exposed Pad  
Pin 1 ID  
1
2
3
4
E2  
E
8
7
6
5
L
b
e/2  
e
Seating  
Plane  
C
A
A3  
A1  
EF_ME  
Table 24. 8-pin, very thin, fine pitch, quad flat package (DFN) mechanical data  
mm  
inches(1)  
Dim.  
Min.  
Typ.  
Max.  
Min.  
Typ.  
Max.  
A
A1  
A3  
b
0.80  
0.00  
0.90  
0.02  
0.20  
0.30  
4.50  
3.65  
3.50  
2.11  
0.80  
0.40  
1.00  
0.05  
0.0315  
0.0000  
0.0354  
0.0008  
0.0079  
0.01181  
0.1771  
0.1437  
0.1378  
0.0831  
0.0315  
0.0157  
0.0394  
0.0020  
0.25  
4.35  
3.50  
3.35  
1.96  
0.35  
4.65  
3.75  
3.65  
2.21  
0.0098  
0.1713  
0.1378  
0.1319  
0.0772  
0.0138  
0.1831  
0.1476  
0.1437  
0.0870  
D
D2  
E
E2  
e
L
0.30  
0.50  
0.08  
0.01181  
0.0197  
0.0031  
ddd  
1. Values in inches are converted from mm and rounded to 4 decimal digits.  
25/30  
Package mechanical data  
QST101  
7.1  
Soldering information  
In accordance with the RoHS European directive, all STMicroelectronics packages have  
been converted to lead-free technology, named ECOPACK™.  
●
ECOPACK™ packages are qualified according to the JEDEC STD-020C compliant  
soldering profile.  
●
Detailed information on the STMicroelectronics ECOPACK™ transition program is  
available on www.st.com/stonline/leadfree/, with specific technical Application notes  
covering the main technical aspects related to lead-free conversion (AN2033, AN2034,  
AN2035, and AN2036).  
Backward and forward compatibility  
The main difference between Pb and Pb-free soldering process is the temperature range.  
●
ECOPACK™ DFN8 packages are fully compatible with Lead (Pb) containing soldering  
process (see application note AN2034).  
Table 25. Soldering compatibility (wave and reflow soldering process)  
Plating material devices  
Sn (pure Tin)  
Pb solder paste  
Pb-free solder paste (1)  
Yes  
Yes  
1. Assemblers must verify that the Pb-package maximum temperature (mentioned on the Inner box label) is  
compatible with their Lead-free soldering process.  
26/30  
QST101  
Part numbering  
8
Part numbering  
Table 26. Ordering information scheme  
Example:  
QST  
1
01  
A
U
6
Device type  
QST = Capacitive touch sensor  
Device sub-family  
1: QTouch (2.4 to 5 V)  
Channel count  
Number of channels  
Pin count  
A: 8 pins  
Package  
U: QFN (dual quad flat no lead)  
Temperature range  
6: –40°C to +85°C  
For a list of available options (speed, package, etc.) or for further information on any aspect  
of this device, please contact your nearest ST Sales Office.  
The category of second Level Interconnect is marked on the package and on the inner box  
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to  
soldering conditions are also marked on the inner box label.  
27/30  
Device revision information  
QST101  
9
Device revision information  
9.1  
Device identification  
Figure 19. Device revision identification  
VFQFPN8 Package  
101 V10  
Table 27. Device revision identification  
Marking  
Device revision  
V10  
First revision  
9.2  
Device revision identification  
The marking on the first line of the package top face identifies the device revision.  
9.2.1  
Revision 1.0  
First device revision.  
28/30  
QST101  
Revision history  
10  
Revision history  
Table 28. Document revision history  
Date  
Revision  
Changes  
01-Apr-2008  
1
First release.  
29/30  
QST101  
Please Read Carefully:  
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the  
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any  
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All ST products are sold pursuant to ST’s terms and conditions of sale.  
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ST and the ST logo are trademarks or registered trademarks of ST in various countries.  
Information in this document supersedes and replaces all information previously supplied.  
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.  
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30/30  
厂商 型号 描述 页数 下载

SAMTEC

 		QST-110-01-F-T [ Board Stacking Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator, Socket, ROHS COMPLIANT ] 1 页

SAMTEC

 		QST-110-01-G-5-MW [ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ] 1 页

SAMTEC

 		QST-110-01-M-T-MW [ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ] 1 页

SAMTEC

 		QST-110-01-S-5-MW [ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ] 1 页

SAMTEC

 		QST-110-01-S-T-MW [ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ] 1 页

SAMTEC

 		QST-110-02-F-T-MW [ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ] 1 页

SAMTEC

 		QST-110-02-G-5-MW [ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ] 1 页

SAMTEC

 		QST-110-02-G-T-MW [ Board Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ] 1 页

SAMTEC

 		QST-110-02-L-5-MW [ Board Connector, 50 Contact(s), 5 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator ] 1 页

SAMTEC

 		QST-110-02-L-T [ Board Stacking Connector, 30 Contact(s), 3 Row(s), Female, Straight, 0.079 inch Pitch, Solder Terminal, Locking, Black Insulator, Socket, ROHS COMPLIANT ] 1 页

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