ADVANCE INFORMATION
CYM9291
[2]
Switching Characteristics Over the Operating Range
133
117
Parameter
Clock
Description
Min.
Max.
Min.
Max.
Unit
t
Clock Cycle Time
7.5
8.6
ns
MHz
ns
CYC
F
Maximum Operating Frequency
Clock HIGH
133
117
MAX
t
t
2.5
2.5
3
3
CH
CL
Clock LOW
ns
Output Times
t
t
t
t
t
t
t
Data Output Valid After CLK Rise
4.4
4.4
4.8
4.8
ns
ns
ns
ns
ns
ns
ns
CDV
EOV
DOH
CHZ
CLZ
[3, 5]
OE LOW to Output Valid
Data Output Hold After CLK Rise
2.3
2.3
0
2.3
2.3
0
[3, 4, 5]
Clock to High-Z
3. 8
3.8
3.8
3.8
[3, 4, 5]
Clock to Low-Z
[3, 4, 5]
OE HIGH to Output High-Z
EOHZ
EOLZ
[3, 4, 5]
OE LOW to Output Low-Z
Set-up Times
t
t
t
t
t
Address Set-Up Before CLK Rise
Data Input Set-Up Before CLK Rise
WE Set-Up Before CLK Rise
ADV/LD Set-Up Before CLK Rise
Chip Selects Set-Up
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
AS
DS
WES
ALS
CES
Hold Times
t
t
t
t
t
Address Hold After CLK Rise
Data Input Hold After CLK Rise
WE Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
AH
DH
WEH
ALH
CEH
ADV/LD Hold after CLK Rise
Chip Selects Hold After CLK Rise
Notes:
2. A/C test conditions assume signal transition time of 2 ns or less, timing reference levels, input pulse levels and output loading shown in AC Test Load for 2.5V
devices.
3.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
4. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
5. This parameter is sampled and not 100% tested.
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