Functional Description
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Maximum Exposure Line Limits
Table 1
Frame/Pixel Rates in QXGA Mode
OV3630 maximum exposure line values are:
Frame Rate (fps)
15
10
5
2.5
•
•
•
QXGA - 1567 lines
PCLK (MHz)
55.2
36.8
18.4
9.2
Register setting: 0x61E = {REG45[5:0] (0x45),
AEC[7:0] (0x10), REG04[1:0] (0x04)}, meaning
REG45[5:0] (0x45) = 0x01, AEC[7:0] (0x10) = 0x87,
REG04[1:0] (0x04)= 0x03
Frame Rate Adjust
XGA - 799 lines
The OV3630 offers three methods for frame rate
adjustment:
Register setting: 0x31E = {REG45[5:0] (0x45),
AEC[7:0] (0x10), REG04[1:0] (0x04)}, meaning
REG45[5:0] (0x45) = 0x00, AEC[7:0] (0x10) = 0xC7,
REG04[1:0] (0x04)= 0x03
•
•
•
Clock prescaler: (see “CLKRC” on page 20)
By changing the system clock divide ratio, the frame
rate and pixel rate will change together. This method
can be used for dividing the frame/pixel rate by: 1/2,
1/3, 1/4 … 1/64 of the input clock rate.
HF - 223 lines
Register setting: 0xDE = {REG45[5:0] (0x45),
AEC[7:0] (0x10), REG04[1:0] (0x04)}, meaning
REG45[5:0] (0x45) = 0x00, AEC[7:0] (0x10) = 0x37,
REG04[1:0] (0x04)= 0x03
Line adjustment: (see “REG2A” on page 23 and see
“FRARL” on page 23)
By adding a dummy pixel timing in each line after
active pixel output, the frame rate can be changed
while leaving the pixel rate as is.
Timing Generator and Control Logic
Vertical sync adjustment:
By adding dummy line periods to the vertical sync
period (see “ADDVSL” on page 23 and see
“ADDVSH” on page 23), the frame rate can be
altered while the pixel rate remains the same.
In general, the timing generator controls the following:
•
•
•
Frame Exposure Mode Timing
Frame Rate Timing
Frame Rate Adjust
SCCB Interface
Frame Exposure Mode Timing
The OV3630 provides an on-chip SCCB serial control port
that allows access to all internal registers, for complete
control and monitoring of OV3630 operation.
The OV3630 supports frame exposure mode. Typically,
the frame exposure mode must work with the aid of an
external shutter.
Refer to OmniVision Technologies Serial Camera Control
Bus (SCCB) Specification for detailed usage of the serial
control port.
The frame exposure pin, FREX (pin C1), is the frame
exposure mode enable pin and the EXP_STB pin (pin C2)
serves as the sensor's exposure start trigger. When the
external master device asserts the FREX pin high, the
sensor array is quickly pre-charged and stays in reset
mode until the EXP_STB pin goes low (sensor exposure
time can be defined as the period between EXP_STB low
and shutter close). After the FREX pin is pulled low, the
video data stream is then clocked to the output port in a
line-by-line manner. After completing one frame of data
output, the OV3630 will output continuous live video data
unless in single frame transfer mode. Figure 21 shows the
detailed timing and Table 11 shows the timing
specifications for this mode.
Slave Operation Mode
The OV3630 can be programmed to operate in slave
mode (default is master mode).
When used as a slave device, COM7[3], CLKRC[6], and
COM2[2] register bits should be set to "1" and the OV3630
will use PWDN and RESET pins as vertical and horizontal
synchronization triggers supplied by a master device. The
master device must provide the following signals:
1.
2.
3.
System clock MCLK to XVCLK pin
Frame Rate Timing
Horizontal sync MHSYNC to RESET pin
Vertical frame sync MVSYNC to PWDN pin
Default frame timing is illustrated in Figure 14, Figure 15
(if PIDL = 0x30), Figure 16 (if PIDL ≠ 0x30), Figure 17,
Figure 18 (if PIDL = 0x30), Figure 19 (if PIDL ≠ 0x30), and
Figure 20. Refer to Table 1 for the actual pixel rate at
different frame rates.
See Figure 7 for slave mode connections and Figure 8 for
detailed timing considerations.
Version 1.2, August 4, 2005
Proprietary to OmniVision Technologies
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