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0ICAW-001-XTP

型号：

0ICAW-001-XTP

品牌：

AMI[ AMI SEMICONDUCTOR ]

页数：

16 页

PDF大小：

563 K

下载PDF手册
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
1. 0 General Description  
Controller Area Network (CAN) is a serial communication protocol, which supports distributed real-time control and multiplexing  
with high safety level. Typical applications of CAN-based networks can be found in automotive and industrial environments.  
The AMIS-42770 Dual-CAN transceiver is the interface between up to two physical bus lines and the protocol controller and will be  
used for serial data interchange between different electronic units at more than one bus line. It can be used for both 12V and 24V  
systems.  
The circuit consists of following blocks:  
•
•
•
•
•
•
Two differential line transmitters  
Two differential line receivers  
Interface to the CAN protocol handler  
Interface to expand the number of CAN busses  
Logic block including repeater function and the feedback suppression  
Thermal shutdown circuit (TSD)  
Due to the wide common-mode voltage range of the receiver inputs, the AMIS-42770 is able to reach outstanding levels of  
electromagnetic susceptibility (EMS). Similarly, extremely low electromagnetic emission (EME) is achieved by the excellent  
matching of the output signals.  
2. 0 Key Features  
•
•
•
•
•
•
•
•
•
•
•
•
Fully compatible with the ISO 11898-2 standard  
Certified “Authentication on CAN Transceiver Conformance (d1.1)”  
Wide range of bus communication speed (up to 1Mbit/s in function of the bus topology)  
Allows low transmit data rate in networks exceeding 1km  
Ideally suited for 12V and 24V industrial and automotive applications  
Low EME: common-mode-choke is no longer required  
Differential receiver with wide common-mode range (+/- 35V) for high EMS  
No disturbance of the bus lines with an un-powered node  
Prolonged dominant time-out function allowing communication speeds down to 1kbit/s  
Thermal protection  
Bus pins protected against transients  
Short circuit proof to supply voltage and ground  
3. 0 Technical Characteristics  
Table 1: Technical Characteristics  
Symbol  
VCANHx  
VCANLx  
Parameter  
Conditions  
0 < VCC < 5.25V; no time limit  
0 < VCC < 5.25V; no time limit  
Min.  
-45  
-45  
1.5  
Max.  
+45  
+45  
3
Unit  
V
DC voltage at pin CANH1/2  
DC voltage at pin CANL1/2  
Differential bus output voltage in dominant state  
V
V
Vi(dif)(bus_dom)  
42.5Ω < RLT < 60Ω  
Guaranteed differential receiver threshold and  
leakage current  
CM-range  
Input common-mode range for comparator  
-35  
+35  
V
Common-mode peak  
Common-mode step  
See Figure 10 and Figure 11(1)  
See Figure 10 and Figure 11(1)  
-1000  
-250  
1000  
250  
mV  
mV  
VCM-peak  
VCM-step  
Note:  
(1) The parameters VCM-peak and VCM-step guarantee low EME.  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
1
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
4. 0 Ordering Information  
Ordering Code (Tubes)  
Ordering Code (Tape)  
Marketing Name  
Package  
Temp. Range  
-40°C…125°C  
0ICAW-001-XTD  
0ICAW-001-XTP  
AMIS-42770 GHA  
SOIC-20 300 GREEN  
5. 0 Block Diagram  
VCC  
12  
POR  
Thermal  
shutdown  
2 x timer  
clock  
13  
19  
18  
AMIS-42770  
CANH2  
CANL2  
CANH1  
Driver  
control  
Driver  
control  
14  
CANL1  
Timer  
Timer  
Logic  
Unit  
Ri(cm)  
2
Ri(cm)  
+
Vcc  
-
/
Vcc  
-
/
2
+
COMP  
COMP  
VCC  
VCC  
VCC  
Ri(cm)  
Ri(cm)  
VCC  
8
5
6
15 16 17  
10  
3
4
7
9
2
VREF  
Rint  
Tx0 Rx0  
ENB1  
Text  
ENB2  
PC20071011.1  
GND  
Figure 1: Block Diagram  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
2
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
6. 0 Typical Application  
6.1 Application Description  
AMIS-42770 is especially designed to provide the link between a CAN controller (protocol IC) and two physical busses. It is able to  
operate in three different modes:  
•
•
•
Dual CAN  
A CAN-bus extender  
A CAN-bus repeater  
6.2 Application Schematics  
VBAT  
CAN BUS 1  
CAN BUS 2  
5V-reg  
CD  
100 nF  
VCC  
Vref  
13  
CANH1  
12  
8
EN1  
EN2  
Rx0  
10  
2
RLT  
60 Ω  
CANL1  
CANH2  
14  
19  
7
AMIS-42770  
Tx0  
4
Text  
RLT  
3
Rint  
60 Ω  
CANL2  
9
18  
5
6
15 16 17  
PC20071011.3  
GND  
Figure 2: Application Diagram CAN-bus Repeater  
VBAT  
CAN BUS 1  
CAN BUS 2  
5V-reg  
CD  
100 nF  
CD  
100 nF  
VCC  
VCC  
Vref  
13  
CANH1  
12  
8
EN1  
10  
2
RLT  
EN2  
Rx0  
60 Ω  
CANL1  
CANH2  
14  
19  
7
µC  
AMIS-42770  
Tx0  
CAN  
con-  
troller  
4
Text  
RLT  
3
Rint  
60 Ω  
CANL2  
9
18  
5
6
15 16 17  
GND  
GND  
PC20071011.5  
Figure 3: Application Diagram Dual-CAN  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
3
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
VBAT  
CAN BUS 1  
CAN BUS 2  
5V-reg  
CD  
CD  
100 nF  
100 nF  
VCC  
VCC  
Vref  
13  
CANH1  
12  
8
EN1  
10  
2
RLT  
EN2  
Rx0  
Tx0  
60 Ω  
CANL1  
CANH2  
14  
19  
7
µC  
AMIS-42770  
CAN  
con-  
troller  
4
Text  
RLT  
3
Rint  
60 Ω  
CANL2  
9
18  
5
6
15 16 17  
GND  
GND  
isolated +5  
CAN BUS 3  
CAN BUS 4  
Dual  
OptoCoupler  
CD  
100 nF  
VCC  
Vref  
CANH1  
12  
8
EN1  
EN2  
Rx0  
Tx0  
13  
10  
2
RLT  
60 Ω  
CANL1  
CANH2  
14  
19  
7
AMIS-42770  
4
Text  
RLT  
3
Rint  
60 Ω  
CANL2  
9
18  
5
6
15 16 17  
PC20071011.7  
GND  
Figure 4: Application Diagram CAN-bus Extender  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
 
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
6.3 Pin Description  
6.3.1 Pin Out (top view)  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
NC  
EN2  
Text  
Tx0  
NC  
CANH2  
CANL2  
GND  
3
4
5
GND  
GND  
Rx0  
GND  
6
GND  
7
CANL1  
CANH1  
VCC  
8
Vref1  
Rint  
9
10  
EN1  
NC  
PC20071011.2  
Figure 5: Pin Configuration  
6.3.2 Pin Description  
Table 2: Pin Out  
Pin  
1
2
3
4
5
6
7
Name  
NC  
ENB2  
Text  
Description  
Not connected  
Enable input, bus system 2; internal pull-up  
Multi-system transmitter Input; internal pull-up  
Transmitter input; internal pull-up  
Ground connection (1)  
Tx0  
GND  
GND  
Rx0  
Ground connection (1)  
Receiver output  
8
9
VREF1  
Rint  
ENB1  
NC  
VCC  
CANH1  
CANL1  
GND  
GND  
GND  
CANL2  
CANH2  
NC  
Reference voltage  
Multi-system receiver output  
Enable input, bus system 1; internal pull-up  
Not connected  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Positive supply voltage  
CANH transceiver I/O bus system 1  
CANL transceiver I/O bus system 1  
Ground connection (1)  
Ground connection (1)  
Ground connection (1)  
CANL transceiver I/O bus system 2  
CANH transceiver I/O bus system 2  
Not connected  
Notes:  
(1) In order to ensure the chip performance, all these pins need to be connected to GND on the PCB.  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
5
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
7. 0 Functional Description  
7.1 Overall Functional Description  
AMIS-42770 is specially designed to provide the link between the protocol IC (CAN controller) and two physical bus lines. Data  
interchange between those two bus lines is realized via the logic unit inside the chip. To provide an independent switch-off of the  
transceiver units for both bus systems by a third device (e.g. the µC), enable-inputs for the corresponding driving and receiving  
sections are provided. As long as both lines are enabled, they appear as one logical bus to all nodes connected to either of them.  
The bus lines can have two logical states, dominant or recessive. A bus is in the recessive state when the driving sections of all  
transceivers connected to the bus are passive. The differential voltage between the two wires is approximately zero. If at least one  
driver is active, the bus changes into the dominant state. This state is represented by a differential voltage greater than a minimum  
threshold and therefore by a current flow through the terminating resistors of the bus line. The recessive state is overwritten by the  
dominant state.  
In case a fault (like short circuit) is present on one of the bus lines, it remains limited to that bus line where it occurs. Data  
interchange from the protocol IC to the other bus system and on this bus system itself can be continued.  
AMIS-42770 can be also used for only one bus system. If the connections for the second bus system are simply left open it serves  
as a single transceiver for an electronic unit. For correct operation, it is necessary to terminate the open bus by the proper  
termination resistor.  
7.2 Logic Unit and CAN Controller Interface  
The logic unit inside AMIS-42770 provides data transfer from/to the digital interface to/from the two busses and from one bus to the  
other bus. The detailed function of the logic unit is described in Table 3.  
All digital input pins, including ENBx, have an internal pull-up resistor to ensure a recessive state when the input is not connected  
or is accidentally interrupted. A dominant state on the bus line is represented by a low-level at the digital interface; a recessive  
state is represented by a high-level.  
Dominant state received on any bus (if enabled) causes a dominant state on both busses, pin Rint and pin Rx0. Dominant signal  
on any of the input pins Tx0 and Text causes transmission of dominant on both bus lines (if enabled).  
Digital inputs Tx0 and Text are used for connecting the internal logic’s of several IC’s to obtain versions with more than two bus  
outputs (see Figure 4: Application Diagram CAN-bus Extender). They have also a direct logical link to pins Rx0 and Rint  
independently on the EN1x pins – dominant on Tx0 is directly transferred to both Rx0 and Rint pins, dominant on Text is only  
transferred to Rx0.  
7.3 Transmitters  
The transceiver includes two transmitters, one for each bus line, and a driver control circuit. Each transmitter is implemented as a  
push and a pull driver. The drivers will be active if the transmission of a dominant bit is required. During the transmission of a  
recessive bit all drivers are passive. The transmitters have a built-in current limiting circuit that protects the driver stages from  
damage caused by accidental short circuit to either positive supply voltage or to ground. Additionally a thermal protection circuit is  
integrated.  
The driver control circuit ensures that the drivers are switched on and off with a controlled slope to limit EME. The driver control  
circuit will be controlled itself by the thermal protection circuit, the timer circuit and the logic unit.  
The enable signal ENBx allows the transmitter to be switched off by a third device (e.g. the µC). In the disabled state (ENBx =  
high) the corresponding transmitter behaves as in the recessive state.  
AMI Semiconductor – October 2007, Rev. 1.0  
6
www.amis.com  
Specifications subject to change without notice  
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
Table 3: Function of the Logic Unit; bold letters describe input signals  
EN1B  
0
EN2B  
0
TX0  
0
TEXT  
0
Bus 1 State  
Bus 2 State  
RX0  
RINT  
dominant  
dominant  
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
1
1
dominant  
dominant  
recessive  
dominant(1)  
dominant  
dominant  
dominant  
recessive  
dominant  
dominant(1)  
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
dominant  
dominant  
dominant  
recessive  
dominant(1)  
recessive  
recessive  
recessive  
recessive  
recessive  
recessive  
dominant(1)  
0
0
0
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
1
1
recessive  
recessive  
recessive  
recessive  
dominant(1)  
recessive  
dominant  
dominant  
dominant  
recessive  
recessive  
dominant(1)  
0
0
0
1
1
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
1
0
1
1
1
recessive  
recessive  
recessive  
recessive  
dominant(1)  
recessive  
recessive  
recessive  
recessive  
recessive  
recessive  
dominant(1)  
0
0
0
1
1
1
0
0
1
1
1
1
Note:  
(1) Dominant detected by the corresponding receiver.  
7.4 Receivers  
Two bus receiving sections sense the states of the bus lines. Each receiver section consists of an input filter and a fast and  
accurate comparator. The aim of the input filter is to improve the immunity against high-frequency disturbances and also to  
convert the voltage at the bus lines CANHx and CANLx, which can vary from –12V to +12V, to voltages in the range 0 to 5V, which  
can be applied to the comparators.  
The output signal of the comparators is gated by the ENBx signal. In the disabled state (ENBX = high), the output signal of the  
comparator will be replaced by a permanently recessive state and does not depend on the bus voltage. In the enabled state the  
receiver signal sent to the logic unit is identical to the comparator output signal.  
7.5 Time-out Counter  
To avoid that the transceiver drives a permanent dominant state on either of the bus lines (blocking all communication), time-out  
function is implemented. Signals on pins Tx0 and Text as well as both bus receivers are connected to the logic unit through  
independent timers. If the input of the timer stays dominant for longer than 25ms (see parameter tdom), it is replaced by a recessive  
signal on the timer output.  
7.6 Feedback Suppression  
The logic unit described in Table 3 constantly ensures that dominant symbols on one bus line are transmitted to the other bus line  
without imposing any priority on either of the lines. This feature would lead to an “interlock” state with permanent dominant signal  
transmitted to both bus lines, if no extra measure is taken.  
Therefore a feedback suppression is included inside the logic unit of the transceiver. This block masks-out reception on that bus  
line, on which a dominant is actively transmitted. The reception becomes active again only with certain delay after the dominant  
transmission on this line is finished.  
AMI Semiconductor – October 2007, Rev. 1.0  
7
www.amis.com  
Specifications subject to change without notice  
 
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
7.7 Power-on-Reset (POR)  
While Vcc voltage is below the POR level, the POR circuit makes sure that:  
•
•
•
•
•
•
•
The counters are kept in the reset mode and stable state without current consumption  
Inputs are disabled (don't care)  
Outputs are high impedant; only Rx0 = high-level  
Analog blocks are in power down  
Oscillator not running and in power down  
CANHx and CANLx are recessive  
VREF output high impedant for POR not released  
7.8 Over Temperature Detection  
A thermal protection circuit is integrated to prevent the transceiver from damage if the junction temperature exceeds thermal  
shutdown level. Because the transmitters dissipate most of the total power, the transmitters will be switched off only to reduce  
power dissipation and IC temperature. All other IC functions continue to operate.  
7.9 Fault Behavior  
A fault like a short circuit is limited to that bus line where it occurs; hence data interchange from the protocol IC to the other bus  
system is not affected.  
When the voltage at the bus lines is going out of the normal operating range (-12V to +12V), the receiver is not allowed to  
erroneously detect a dominant state.  
7.10 Short Circuits  
As specified in the maximum ratings, short circuits of the bus wires CANHx and CANLx to the positive supply voltage Vbat or to  
ground must not destroy the transceiver. A short circuit between CANHx and CANLx must not destroy the IC as well.  
7.11 Faulty Supply  
In case of a faulty supply (missing connection of the electronic unit or the transceiver to ground, missing connection of the  
electronic unit to Vbat or missing connection of the transceiver to Vcc), the power supply module of the electronic unit will operate  
such that the transceiver is not supplied, i.e. the voltage Vcc is below the POR level. In this condition the bus connections of the  
transceiver must be in the POR state.  
If the ground line of the electronic unit is interrupted, Vbat may be applied to the Vcc pin (measured relative to the original ground  
potential, to which the other units on the bus are connected).  
7.12 Reverse Electronic Unit (ECU) Supply  
If the connections for ground and supply voltage of an electronic unit (ECU) (max. 50V) which provides Vcc for the transceiver are  
exchanged, this transceiver has a ground potential which may be up to 50V higher than that of the other transceivers. In this case  
no transceiver must be destroyed even if several of them are connected via the bus system.  
Any exchange among the six connections CANH1, CANH2, CANL1, CANL2, ground, and supply voltage of the electronic unit at  
the connector of the unit must never lead to the destruction of any transceiver of the bus system.  
AMI Semiconductor – October 2007, Rev. 1.0  
8
www.amis.com  
Specifications subject to change without notice  
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
8. 0 Electrical Characteristics  
8.1 Definitions  
All voltages are referenced to GND. Positive currents flow into the IC. Sinking current means that the current is flowing into the  
pin. Sourcing current means that the current is flowing out of the pin.  
8.2 Absolute Maximum Ratings  
Stresses above those listed in Table 4 may cause permanent device failure. Exposure to absolute maximum ratings for extended  
periods may affect device reliability.  
Table 4: Absolute Maximum Ratings  
Symbol  
VCC  
Parameter  
Conditions  
Min.  
-0.3  
-45  
Max.  
+7  
Unit  
V
Supply voltage  
DC voltage at pin CANH1/2  
DC voltage at pin CANL1/2  
0 < VCC < 5.25V; no time limit  
0 < VCC < 5.25V; no time limit  
+45  
+45  
V
VCANHx  
VCANLx  
-45  
V
DC voltage at digital IO pins (EN1B, EN2B, Rint, Rx0,  
Text, Tx0)  
-0.3  
VCC + 0.3  
V
VdigIO  
DC voltage at pin VREF  
-0.3  
-150  
-150  
VCC + 0.3  
+150  
V
V
V
VREF  
Transient voltage at pin CANH1/2  
Transient voltage at pin CANL1/2  
Note 1  
Note 1  
Vtran(CANHx)  
Vtran(CANLx)  
Vesd(CANLx/CANHx)  
+150  
Note 2  
Note 4  
Note 2  
Note 4  
-4  
-500  
-2  
+4  
+500  
+2  
kV  
V
kV  
V
ESD voltage at CANH1/2 and CANL1/2 pins  
ESD voltage at all other pins  
Vesd  
-250  
+250  
Latch-up  
Tstg  
Static latch-up at all pins  
Storage temperature  
Note 3  
100  
mA  
°C  
°C  
°C  
-55  
-40  
-40  
+155  
+125  
+150  
Ambient temperature  
Tamb  
Maximum junction temperature  
Tjunc  
Notes:  
(1) Applied transient waveforms in accordance with “ISO 7637 part 3”, test pulses 1, 2, 3a, and 3b (see Figure 6).  
(2) Standardized human body model (HBM) ESD pulses in accordance to MIL883 method 3015. Supply pin 8 is ±2 kV.  
(3) Static latch-up immunity: static latch-up protection level when tested according to EIA/JESD78.  
(4) Standardized charged device model ESD pulses when tested according to EOS/ESD DS5.3-1993.  
8.3 Thermal Characteristics  
Table 5: Thermal Characteristics  
Symbol  
Parameter  
Conditions  
In free air  
In free air  
Value  
Unit  
Thermal resistance from junction to ambient in SO20 package  
Thermal resistance from junction to substrate of bare die  
85  
45  
K/W  
K/W  
Rth(vj-a)  
Rth(vj-s  
)
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
9
 
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
8.4 DC Characteristics  
VCC = 4.75 to 5.25V; Tjunc = -40 to +150°C; RLT =60Ω unless specified otherwise.  
Table 6: DC and Timing Characteristics  
Symbol  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Unit  
Supply (pin VCC  
)
Supply current, no loads on digital outputs,  
both busses enabled  
Power-on-reset level on VCC  
Dominant transmitted  
Recessive transmitted  
45  
137.5  
19.5  
4.7  
mA  
mA  
V
ICC  
PORL_VCC  
2.2  
Digital Inputs (Tx0, Text, EN1B, EN2B)  
VIH  
VIL  
IIH  
IIL  
Ci  
High-level input voltage  
Low-level input voltage  
High-level input current  
Low-level input current  
Input capacitance  
0.7 x VCC  
-0.3  
-5  
-
-
0
-200  
5
VCC  
0.3 x VCC  
+5  
-350  
10  
V
V
µA  
µA  
pF  
VIN = VCC  
VIN = 0V  
Not tested  
-75  
-
Digital Outputs (pin Rx0, Rint)  
Ioh  
Iol  
High-level output current  
Low-level output current  
Vo = 0.7 x VCC  
Vo = 0.3 x VCC  
-5  
5
-10  
10  
-15  
15  
mA  
mA  
Reference Voltage Output (pin VREF1  
)
VREF  
Reference output voltage  
Reference output voltage for full common  
mode range  
0.45 x VCC  
0.40 x VCC  
0.50 x VCC  
0.50 x VCC  
0.55 x VCC  
0.60 x VCC  
V
V
-50µA < IVREF < +50µA  
-35V <VCANHx< +35V;  
-35V <VCANLx< +35V  
VREF_CM  
Bus Lines (pins CANH1/2 and CANL1/2)  
Vo(reces)(CANHx) Recessive bus voltage at pin CANH1/2  
Vo(reces)(CANLx)  
VTx0 = VCC; no load  
VTx0 = VCC; no load  
-35V < VCANHx < +35V;  
0V < VCC < 5.25V  
-35V < VCANLx < +35V;  
0V < VCC < 5.25V  
VTx0=0V  
2.0  
2.0  
2.5  
2.5  
3.0  
3.0  
V
V
Recessive bus voltage at pin CANL1/2  
Recessive output current at pin CANH1/2  
Io(reces) (CANHx)  
-2.5  
-2.5  
-
-
+2.5  
+2.5  
mA  
mA  
Io(reces) (CANLx)  
Vo(dom) (CANHx)  
Vo(dom) (CANLx)  
Recessive output current at pin CANL1/2  
Dominant output voltage at pin CANH1/2  
Dominant output voltage at pin CANL1/2  
3.0  
0. 5  
3.6  
1.4  
4.25  
1.75  
V
V
VTx0=0V  
VTx0 = 0V; dominant;  
42.5Ω < RLT < 60Ω  
VTxD = VCC; recessive;  
no load  
1.5  
2.25  
0
3.0  
V
Differential bus output voltage (VCANHx  
VCANLx  
-
Vi(dif) (bus)  
)
-120  
+50  
mV  
Io(sc) (CANHx)  
Io(sc) (CANLx)  
Short circuit output current at pin CANH1/2  
Short circuit output current at pin CANL1/2  
VCANHx = 0V;VTx0 = 0V  
VCANLx = 36V; VTx0 = 0V  
-5V < VCANLx < +12V;  
-5V < VCANHx < +12V;  
see Figure 7  
-35V < VCANLx < +35V;  
-35V < VCANHx < +35V;  
see Figure 7  
-45  
45  
-70  
70  
-120  
120  
mA  
mA  
Vi(dif)(th)  
Differential receiver threshold voltage  
0.5  
0.3  
50  
0.7  
0.7  
70  
0.9  
1.05  
100  
V
V
Differential receiver threshold voltage for  
high common-mode  
Vihcm(dif) (th)  
-35V < VCANL < +35V;  
-35V < VCANH < +35V;  
see Figure 7  
Vi(dif) (hys)  
Differential receiver input voltage hysteresis  
mV  
Common-mode input resistance at pin  
CANH1/2  
Common-mode input resistance at pin  
CANL1/2  
Matching between pin CANH1/2 and pin  
CANL1/2 common-mode input resistance  
Differential input resistance  
Input capacitance at pin CANH1/2  
Input capacitance at pin CANL1/2  
Differential input capacitance  
Ri(cm)(CANHx)  
Ri(cm) (CANLx)  
Ri(cm)(m)  
15  
15  
26  
26  
0
37  
37  
+3  
KΩ  
KΩ  
%
V
CANHx = VCANLx  
-3  
Ri(dif)  
25  
50  
7.5  
7.5  
75  
20  
20  
10  
KΩ  
pF  
pF  
pF  
Ci(CANHx)  
Ci(CANLx)  
Ci(dif)  
VTx0 = VCC; not tested  
VTx0 = VCC; not tested  
VTx0 = VCC; not tested  
VCC < PORL_VCC;  
-5.25V < VCANHx < 5.25V  
VCC < PORL_VCC;  
3.75  
ILI(CANHx)  
ILI(CANLx)  
VCM-peak  
VCM-step  
Input leakage current at pin CANH1/2  
Input leakage current at pin CANL1/2  
-350  
-350  
170  
170  
350  
350  
µA  
µA  
-5.25V < VCANLx < 5.25V  
Common-mode peak during transition from  
dom → rec or rec → dom  
Difference in common-mode between  
dominant and recessive state  
See Figure 11  
See Figure 11  
-1000  
-250  
1000  
250  
mV  
mV  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
10  
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
Table 6: DC and Timing Characteristics (Continued)  
Symbol  
Thermal Shutdown  
Tj(sd) Shutdown junction temperature  
Parameter  
Conditions  
Min.  
Typ.  
Max.  
Unit  
150  
°C  
Timing Characteristics (see Figure 8: Test Circuit for Timing Characteristics and Figure 9: Timing Diagram for AC Characteristics)  
td(Tx-BUSon)  
td(Tx-BUSoff)  
td(BUSon-RX)  
td(BUSoff-RX)  
td(ENxB)  
Delay Tx0/Text to bus active  
Delay Tx0/Text to bus inactive  
Delay bus active to Rx0/Rint  
Delay bus inactive to Rx0/Rint  
Delay from EN1B to bus active/inactive  
Delay from Tx0 to Rx0/Rint and from Text to  
Rx0 (direct logical path)  
40  
30  
25  
65  
85  
60  
55  
100  
100  
120  
115  
115  
145  
200  
ns  
ns  
ns  
ns  
ns  
td(Tx-Rx)  
tdom  
15pF on the digital output  
4
10  
25  
35  
45  
ns  
ms  
ns  
Time out counter interval  
15  
5+  
td(BUSon-RX)  
td(FBS)  
Delay for feedback suppression release  
300  
8.5 Measurement Set-ups and Definitions  
Schematics are given for single CAN transceiver.  
+5V  
100 nF  
VCC  
Vref  
1 nF  
1 nF  
CANH1  
12  
8
13  
Text  
Rint  
Transient  
Generator  
3
9
CANL1  
CANH2  
14  
19  
AMIS-42770  
Tx0  
4
7
Rx0  
CANL2  
18  
2
10  
17 16 15  
6
5
GND  
PC20071011.8  
EN1  
EN2  
Figure 6: Test Circuit for Automotive Transients  
VRxD  
High  
Low  
Hysteresis  
PC20040829.7  
0,9  
0,5  
Vi(dif)(hys)  
Figure 7: Hysteresis of the Receiver  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
11  
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
+5V  
100 nF  
VCC  
12  
Vref  
13  
CANH1  
8
Text  
Rint  
RLT  
CLT  
3
60 Ω  
100 pF  
CANL1  
CANH2  
14  
19  
9
AMIS-42770  
Tx0  
CLT  
RLT  
4
7
100 pF  
60 Ω  
Rx0  
CANL2  
18  
5
2
10  
17 16 15  
6
GND  
PC20071011.9  
EN1  
EN2  
Figure 8: Test Circuit for Timing Characteristics  
Tx0  
Text  
0,7 VCC  
0,3 VCC  
VCANx-BUS  
VCANHx  
VCANLx  
VDIFF  
=
VCANHx  
- VCANLx  
dominant  
recessive  
5V  
0,9 V  
0,9 V  
0,5 V  
0,5 V  
0V  
tPD(H)  
Rx0  
Rint  
0,7 VCC  
0,7 VCC  
0,3 VCC  
0,3 VCC  
td(BUSon-Rx)  
td(BUSoff-Rx)  
td(Tx-Rx)  
td(Tx-Rx)  
PC20071012.1  
td(Tx-BUSon)  
td(Tx-BUSoff)  
Figure 9: Timing Diagram for AC Characteristics  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
12  
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
+5V  
100 nF  
VCC  
12  
Vref  
13  
6.2 kΩ  
CANH1  
8
10 nF  
Text  
Rint  
3
Active Probe  
Spectrum Anayzer  
CANL1  
CANH2  
14  
19  
9
6.2 kΩ  
30 Ω  
AMIS-42770  
Tx0  
30 Ω  
4
7
Gen  
Rx0  
CANL2  
18  
5
2
10  
17 16 15  
6
47 nF  
GND  
EN1  
EN2  
PC20071011.10  
Figure 10: Basic Test Set-up for Electromagnetic Measurement  
CANHx  
CANLx  
recessive  
VCM-step  
VCM-peak  
Vi(com) = 0.5 *  
(VCANHx + VCANLx  
)
PD20070614.1  
VCM-peak  
Figure 11: Common-mode Voltage Peaks (see measurement set-up Figure 10)  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
13  
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
9. 0 Package Outline  
SOIC-20: Plastic small outline; 20 leads; body width 300mil.  
AMI Semiconductor – October 2007, Rev. 1.0  
14  
www.amis.com  
Specifications subject to change without notice  
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
10. 0 Soldering  
10.1 Introduction to Soldering Surface Mount Packages  
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in the AMIS  
“Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that  
is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards  
(PCBs) with high population densities. In these situations re-flow soldering is often used.  
10.2 Re-flow Soldering  
Re-flow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the PCB by  
screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for  
example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between  
100 and 200 seconds depending on heating method. Typical re-flow peak temperatures range from 215 to 250°C. The top-surface  
temperature of the packages should preferably be kept below 230°C.  
10.3 Wave Soldering  
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or PCBs with a high component  
density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering  
method was specifically developed.  
If wave soldering is used the following conditions must be observed for optimal results:  
•
Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth  
laminar wave.  
•
For packages with leads on two sides and a pitch (e):  
Larger than or equal to 1.27mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of  
the PCB;  
Smaller than 1.27mm, the footprint longitudinal axis must be parallel to the transport direction of the PCB. The  
footprint must incorporate solder thieves at the downstream end.  
•
For packages with leads on four sides, the footprint must be placed at a 45º angle to the transport direction of the PCB.  
The footprint must incorporate solder thieves downstream and at the side corners.  
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by  
screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is  
four seconds at 250°C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.  
10.4 Manual Soldering  
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24V or less) soldering iron applied to  
the flat part of the lead. Contact time must be limited to 10 seconds at up to 300°C.  
When using a dedicated tool, all other leads can be soldered in one operation within two to five seconds between 270 and 320°C.  
Table 7: Soldering Process  
Soldering Method  
Package  
Wave  
Re-flow(1)  
Suitable  
Suitable  
Suitable  
Suitable  
Suitable  
BGA, SQFP  
Not suitable  
Not suitable (2)  
HLQFP, HSQFP, HSOP, HTSSOP, SMS  
PLCC (3) , SO, SOJ  
Suitable  
LQFP, QFP, TQFP  
Not recommended (3)(4)  
Not recommended (5)  
SSOP, TSSOP, VSO  
Notes:  
1.  
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size  
of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For  
details, refer to the drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods.”  
These packages are not suitable for wave soldering as a solder joint between the PCB and heatsink (at bottom version) can not be achieved, and as solder may  
stick to the heatsink (on top version).  
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder  
thieves downstream and at the side corners.  
Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8mm; it is definitely not suitable for packages with a  
pitch (e) equal to or smaller than 0.65mm.  
2.  
3.  
4.  
5.  
Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65mm; it is definitely not suitable for packages with a  
pitch (e) equal to or smaller than 0.5mm.  
AMI Semiconductor – October 2007, Rev. 1.0  
www.amis.com Specifications subject to change without notice  
15  
AMIS-42770 Dual High-Speed CAN Transceiver  
For Long Networks  
Data Sheet  
11. 0 Revision History  
Revision  
Date  
Description  
1.0  
October 2007  
Initial version  
12. 0 Company or Product Inquiries  
For more information about AMI Semiconductor’s products or services visit our Web site at http://www.amis.com/sales.  
Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express,  
statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes  
no warranty of merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at any time and  
without notice. AMI Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual  
environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without  
additional processing by AMIS for such applications. Copyright ©2007 AMI Semiconductor, Inc.  
AMI Semiconductor – October 2007, Rev. 1.0  
16  
www.amis.com  
Specifications subject to change without notice  
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