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CYIS1SM1000AA-HFC

型号：

CYIS1SM1000AA-HFC

品牌：

ONSEMI[ ONSEMI ]

页数：

24 页

PDF大小：

953 K

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STAR-1000  
Datasheet  
STAR-1000  
1 M Pixel  
Radiation - Hard  
CMOS image sensor  
Datasheets  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 1 of 24  
STAR-1000  
Datasheet  
Table of contents  
1.  
2.  
SENSOR DESCRIPTION ............................................................................................................................... 4  
1.1.  
The pixel array........................................................................................................................................ 5  
Addressing logic..................................................................................................................................... 5  
The column amplifiers ........................................................................................................................... 6  
The output amplifier and analog multiplexer ........................................................................................ 6  
The ADC ................................................................................................................................................ 6  
1.2.  
1.3.  
1.4.  
1.5.  
IMAGE SENSOR SPECIFICATIONS........................................................................................................... 7  
2.1.  
General specifications ............................................................................................................................ 7  
Electro-optical specifications................................................................................................................. 7  
Spectral response curve.......................................................................................................................... 9  
Photo-voltaic response ........................................................................................................................... 9  
Absolute maximum ratings .................................................................................................................. 10  
DC operating conditions ...................................................................................................................... 10  
2.2.  
2.3.  
2.4.  
2.5.  
2.6.  
3.  
TIMING AND CONTROL SIGNALS ......................................................................................................... 11  
3.1.  
3.2.  
Row selection and reset timing............................................................................................................ 11  
Pixel read-out timing............................................................................................................................ 13  
4.  
5.  
PIN LIST........................................................................................................................................................ 14  
PACKAGING AND GEOMETRICAL CONSTRAINTS ........................................................................... 19  
5.1.  
5.2.  
Package drawing................................................................................................................................... 19  
Die alignment ....................................................................................................................................... 20  
6.  
ORDERING INFORMATION...................................................................................................................... 21  
APPENDIX A:  
APPENDIX B:  
STAR-1000 EVALUATION SYSTEM ............................................................................... 22  
FREQUENTLY ASKED QUESTIONS............................................................................... 23  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 2 of 24  
STAR-1000  
Datasheet  
Document history record  
Issue  
Date  
Description of changes  
6.1 4th April, 2003  
p6: Table 1: image sensor specs updated.  
p8: Spectral response curve and photovoltaic  
response curve added.  
p18: Package drawing added.  
p19: Appendix A added.  
p20: Appendix B added.  
6.2 23rd April, 2003  
6.3 8th July, 2003  
p6: Table 1: image sensor specs updated.  
p8: Photovoltaic response curve updated.  
p17: Table 9: VDD_ANA connected  
internally…  
p6: Table 2: values updated.  
p9: Table 3 and 4 added.  
p13: Pin connection drawing added.  
p14: Table 7 updated.  
p16: Notes added.  
p17: Package drawing updated.  
p18: Die alignment added.  
6.4 27th September 2004 p1: Layout changed.  
p7: Table 2 updated.  
p10: Table 3 updated.  
p12: Table 5: f: R changed into LD_Y  
p17: Table 7: Pin 58. Description added.  
p20: Figure 5 updated.  
6.5 4th January 2005  
Added equivalent Cypress part numbers and  
Cypress logo.  
Added Cypress Document # 38-05714 Rev **  
in the document footer.  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 3 of 24  
STAR-1000  
Datasheet  
1. Sensor description  
The STAR-1000 is a CMOS image sensor with 1024 by 1024 pixels on a 15-µm  
pitch. It features on-chip Fixed Pattern Noise (FPN) correction, a programmable gain  
amplifier and a 10-bit Analog to Digital Converter (ADC).  
All circuits are designed using the radiation tolerant design rules for CMOS image  
sensors to allow a high tolerance against total dose effects.  
Registers that can be directly accessed by the external controller contain the X- and  
Y-addresses of the pixels to be read. This architecture provides flexible operation and  
allows different operation modes like (multiple) windowing, sub sampling, etc.  
The image sensor contains five sections: the pixel array, the X-and Y addressing  
logic, the column amplifiers, the output amplifier and the ADC. Figure 1 shows an  
outline diagram of the sensor, including an indication of the main control signals. The  
following paragraphs explain in more detail the function and operation of the different  
imager parts.  
Reset  
Reset DS  
Vref  
Pixel Array  
10  
1024  
1024 x 1024 pixels  
Rst  
D0 … D9  
Clk ADC  
Ain  
Col  
10-bit ADC  
Y address  
decoder  
Ld  
Y
Rst  
Rd  
10  
1024  
Rd  
and logic  
A0 … A9  
10  
1024  
S
R
Column amplifiers  
1024  
1024  
Rst  
Sig  
Progr. gain  
amplifier  
1024  
1024  
Aout  
Clk  
X
Buffer  
X register  
10  
X Address Decoder  
Ld  
X
Figure 1: Image sensor outline diagram  
Part Numbers  
Color or B/W  
STAR-1000  
B&W  
CYIISM1000AA-HFC -(PRELIMINARY)  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 4 of 24  
STAR-1000  
Datasheet  
1.1.  
The pixel array  
The pixel array contains 1024 by 1024 active pixels at 15µm pitch. Each pixel  
contains one photo diode and three transistors (Figure 2).  
The photo diode is always in reverse bias. At the beginning of the integration cycle a  
pulse is applied to the reset line (gate of T1) bringing the cathode of D1 to the reset  
voltage level. During the integration period photon-generated electrons accumulate  
T1  
Read  
Reset  
T2  
T3  
Figure 2: Active pixel electrical diagram  
on the diode capacitance, reducing the voltage on the gate of T2. The real  
illumination-dependent signal is the different between the reset level and the output  
level after integration. This difference is made in the column amplifiers. T2 acts as a  
source follower and T3 allows connection of the pixel signal (reset level and output  
level) to the vertical output bus.  
The reset-lines and the read-lines of the pixels in a row are connected together to the  
Y-decoder logic; the outputs of the pixels in a column are connected together to a  
column amplifier.  
1.2.  
Addressing logic  
The addressing logic allows direct addressing of rows and columns. Instead of the  
one-hot shift registers that are often used, address decoders are implemented. One  
can select a line by presenting the required address to the address input of the device  
and latching it to the Y-decoder logic. Presenting the X-address to the device address  
input and latching it to the X-address decoder can select a column.  
A typical line read out sequence will first select a line by applying the Y-address to  
the Y-decoder. Activation of the “LD_Y” input on the Y-logic will connect the pixel  
outputs of the selected line to the column amplifiers. The individual column amplifier  
outputs can be connected to the output amplifier by applying the respective X-  
addresses to the X address decoder. Applying the appropriate Y-address to the Y-  
decoder and activating the “Reset” input reset a line. The integration time of a row is  
the time between the last reset of this row and time when it is selected for read-out.  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
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Page 5 of 24  
STAR-1000  
Datasheet  
The Y-decoder logic has two different reset inputs: “RESET” and “RESET_DS”.  
Activation of “RESET” will reset the pixel to the Vdd level; activation of  
“RESET_DS” will reset the pixel to the voltage level on the “VREF” input. This  
feature allows the application of the so-called dual slope integration (see APPENDIX  
B). If dual slope integration is not needed “VREF” can be tied to Vdd and  
“RESET_DS” must never be activated.  
1.3.  
The column amplifiers  
All outputs from the pixels in a column are connected in parallel to a column  
amplifier. This amplifier samples the output voltage and the reset level of the pixel  
whose row is selected at that moment and presents these voltage levels to the output  
amplifier. As a result the pixels are always reset immediately after read-out as part of  
the sample procedure and the maximum integration time of a pixel is the time  
between two read cycles.  
1.4.  
The output amplifier and analog multiplexer  
The output amplifier combines subtraction of pixel signal level from reset level with a  
programmable gain amplifier. Since the amplifier is AC coupled it also contains a  
provision to maintain and restore the proper DC level.  
An analogue signal multiplexer feeds the pixel signal to the final unity gain buffer to  
provide the required drive capability. Apart from the pixel signal also three other  
external analogue signals can be fed to the output buffer. All these signals can be  
digitalised by the on-chip ADC if the output of this buffer is externally connected to  
the input of the ADC.  
The purpose of the additional analogue inputs (“A_IN1”, “A_IN2” and “A_IN3”) is  
to allow a possibility to process other analogue signals through the image sensors  
signal path. These signals can thus be converted by the ADC and processed by the  
image controller FPGA. The additional analogue inputs are intended for low  
frequency or DC signals and have a reduced bandwidth, compared with the image  
signal path.  
1.5.  
The ADC  
The image sensor has a 10-bit ADC that is electrically separated from the rest of the  
image sensor circuits and can be powered down if an external ADC is used. The  
conversion takes place at the falling edge of the clock and the output pins can be  
disabled to allow operation of the device in a bus structure.  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 6 of 24  
STAR-1000  
Datasheet  
2. Image sensor specifications  
2.1.  
General specifications  
Table 1: General specification of the STAR-1000 sensor  
Parameter  
Specification  
Comment  
Detector technology  
Pixel structure  
Photodiode  
CMOS Active Pixel Sensor  
3-transistor active pixel  
High fill factor photodiode  
1024 x 1024 pixels  
Radiation-tolerant pixel design.  
Using N-well technique  
Sensitive area  
format  
15 x15 µm2  
Pixel size  
Pixel output rate  
12 MHz  
Speed can be exchanged for power  
consumption  
Windowing  
X- and Y- addressing random  
programmable  
Electronic shutter  
Electronic rolling shutter.  
Range: 1 : 1024  
Integration time is variable in time steps  
equal to the row readout time.  
> 230Krad (Si)  
Pixel test structures with a similar design  
have shown total dose tolerance up to  
several Mrad. Radiation tests on similar  
image sensor were performed up to 230  
Krad.  
Total Dose  
Radiation tolerance  
Expected Equivalent  
fluence at 10 MeV  
3.1010 proton/cm2  
TBD.  
SEL threshold  
> 28 MeV cm3 mg-1  
A similar design was tested up to 28 MeV  
without any latch up noticeable.  
No other evaluations have been done yet.  
2.2.  
Electro-optical specifications  
Table 2: Electro-optical specifications of the STAR-1000 sensor  
Parameter  
Value  
Typical value  
400 - 1000  
Comment  
Unit  
Spectral range  
Quantum efficiency x  
fill factor  
nm  
Average over the visual range. See  
spectral response curve.  
20%  
Full well capacity  
135.000  
e-  
Cypress Semiconductor Corporation 3901 North First Street  
San Jose, CA 95134 408-943-2600  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
Page 7 of 24  
STAR-1000  
Datasheet  
Parameter  
Value  
Comment  
Typical value  
Unit  
Saturation capacity to  
meet non-linearity  
within + 5%  
99.000  
e-  
Output signal swing  
Conversion gain  
kTC noise  
1.1  
11.4  
35  
V
µV/e-  
e-  
Dynamic Range  
Fixed Pattern Noise  
72  
dB  
Local: 1σ < 0.30%  
Global: 1 σ <0.56%  
of full well  
Photo Response Non-  
uniformity at Qsat/2  
(RMS)  
Local: 1σ < 0.67%  
Global: σ <3.93%  
of full well  
Average Dark Current  
at 293 K  
223  
pA/cm2  
e- / s  
Dark current signal  
DSNU signal  
3135  
1.055 % of Vsat  
Vertical: 16 %  
Optical cross-talk  
at 600 nm  
Horizontal: 17.5 %  
Anti-blooming capacity  
Output amplifier gain  
x 1000  
x1, x2.47, x4.59 and x8.64  
9.5  
Controlled by 2 bits  
Analogue input  
bandwidth  
MHz  
V
Analogue input signal  
range  
0.1 to 4.9  
10  
Analog-Digital  
converter  
Radiation-tolerant version of the  
ADC on Ibis4 and other image  
sensors.  
Bit  
ADC Differential Non-  
Linearity (DNL)  
<= ±3.5  
<= ±5.8  
5
LSB  
LSB  
V
ADC Integral Non-  
Linearity (INL)  
Integral non-linearity of ADC is  
better than linearity of image sensor.  
Supply voltage  
Digital input signals are 3.3 V  
compatible  
Power Dissipation  
< 350  
< 100  
With internal ADC powered.  
Without internal ADC powered.  
mW  
Both values measured at nominal  
speed (12 MHz).  
Cypress Semiconductor Corporation 3901 North First Street  
San Jose, CA 95134 408-943-2600  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
Page 8 of 24  
STAR-1000  
Datasheet  
2.3.  
Spectral response curve  
0 .1 6  
0 .1 4  
0 .1 2  
0 .1  
Q E 0 .3  
Q E 0 .2  
0 .0 8  
0 .0 6  
0 .0 4  
0 .0 2  
0
Q E 0 .1  
Q E  
Q E 0 .0 1  
4 0 0  
5 0 0  
6 0 0  
7 0 0  
8 0 0  
9 0 0  
1 0 0 0  
W a v e le n g h t [n m ]  
2.4.  
Photo-voltaic response  
1.2  
1
0.8  
0.6  
0.4  
0.2  
0
0
20000  
40000  
60000  
80000 100000 120000 140000 160000 180000  
Number of electrons  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 9 of 24  
STAR-1000  
Datasheet  
2.5.  
Absolute maximum ratings  
Table 3:Absolute maximum ratings  
Characteristics  
Symbol Limits  
Min Max  
-0.5 +7  
Units Remarks  
Any supply voltage  
Voltage on any input  
terminal  
V
V
Vdd +  
-0.5  
0.5  
Operating  
Temperature range to be confirmed by  
0
+60  
°C  
°C  
°C  
temperature  
evaluation testing  
Storage temperature  
Not longer than 1 hour. Temperature  
range to be confirmed by evaluation  
testing  
Maximum solder temperature to be  
confirmed by evaluation testing  
-10  
NA  
+60  
Soldering  
260  
temperature  
(TBC)  
2.6.  
DC operating conditions  
Table 4: DC operating conditions  
Symbol  
Parameter  
Limits  
Typ  
Units  
Min  
Max  
VDDA  
VDDD  
Analog supply of the image core.  
Digital supply of the image core.  
5
5
5
5
V
V
V
V
VDD_ADC_ANA Analog supply of the ADC circuitry.  
VDD_ADC_DIG Digital supply of the ADC circuitry.  
VDD_DIG_OUT Power supply of ADC digital output  
5
5
V
stage.  
VRES  
VREF  
GNDA  
GNDD  
Reset level for RESET signal.  
Reset level for RESET_DS signal.  
Analog ground of the image core.  
Digital ground of the image core.  
V
V
V
V
V
V
V
V
V
V
4
5
0
0
0
0
GND_ADC_ANA Analog ground of the ADC circuitry.  
GND_ADC_DIG Digital ground of the ADC circuitry.  
VIH  
VIL  
Logical ‘1’ input voltage.  
Logical ‘0’ input voltage.  
Logical ‘1’ output voltage.  
Logical ‘0’ output voltage.  
1.8  
0
VDDD  
1
VDDD  
1
VOH  
VOL  
4.25  
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Page 10 of 24  
STAR-1000  
Datasheet  
3. Timing and control signals  
The pixels addressing is done by direct addressing of rows and columns. This  
approach has the advantage of full flexibility when accessing the pixel array: multiple  
windowing and sub-sampled read-out are possible by proper programming.  
The following paragraphs clarify the timing for row- and column readout.  
3.1.  
Row selection and reset timing  
Figure 3 shows the timing of the line sequence control signals. The timing constraints  
are given in table 5.  
The address, presented at the address IO pins (A0…A9) is latched in with the LD-Y  
pulse (active low). After latching; the external controller can already produce a new  
A0 … A9  
Reset address  
Read address  
k
l
m
k
l
m
LD Y\  
Internal  
S
Row selected for readout  
a
Row selected for reset  
b
h
d
c
i
f
g
Reset  
R
d
e
b
CAL  
(once each  
frame)  
Row readout  
Time available for readout of Row Y-1  
Idle  
Time available for X-readout of Row Y  
Figure 3: Line selection and reset sequence  
address.  
Latching in a Y-address selects the addressed row and connects the pixel outputs of  
that row to the column amplifiers. Through the sequence of the S and R pulse and the  
Reset pulse in-between the pixel output signal and reset level are sampled and  
produced at the output of the column amplifier (to do the FPN double sampling  
correction).  
At this time horizontal read-out of the selected row can start and another row can be  
reset to effectuate reduced integration time (electronic rolling shutter).  
Table 5 shows the timing constraints for the horizontal or line-select timing.  
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Page 11 of 24  
STAR-1000  
Datasheet  
Table 5: Timing constraints of line sequence  
Symbol Min. Typ.  
Description  
a
Delay between selection of a new row and falling edge on S.  
Minimal value: For maximum speed a new row can already be  
selected during X-readout of the previous row.  
3.6 µs  
b
c
d
e
f
Duration of S and R pulse.  
0.4 µs  
0
100 ns  
Delay between falling edge of S and rising edge of Reset.  
Minimum duration of Reset pulse.  
200 ns  
1.6 µs  
0
Delay between falling edge of Reset and falling edge of R.  
100 ns  
100 ns  
200 ns  
1 µs  
Minimum delay between falling edge on LD_Y and rising edge of  
Reset.  
g
Minimum required extension of Y-address after falling edge of reset  
pulse.  
h
100 ns  
Position of Cal pulse after rising edge of S.  
The cal pulse must only be given once per frame.  
i
k
l
100 ns  
10 ns  
20 ns  
10 ns  
Duration of Cal pulse.  
Address set-up time.  
Load register value.  
m
Address stable after load.  
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Page 12 of 24  
STAR-1000  
Datasheet  
3.2.  
Pixel read-out timing  
Figure 4 shows the timing of the pixel readout sequence. The external digital  
controller presents a column address that is latched in by the rising edge of the LD_X  
pulse. After decoding the X-address the column selection is clocked in the X-register  
Row idle time  
A0 … A9  
X1  
X2  
X3  
X4  
X5  
X6  
X7  
X8  
LD  
X
a
b
CLK X  
Analog  
output  
Undefined output level  
X1  
X2  
X3  
X4  
X5  
X6  
CLK ADC  
D9 … D0  
c
X1  
X2  
X3  
X4  
Figure 4: Column selection and read-out sequence  
by CLK-X. The output amplifier uses the same pulse to subtract the pixel output level  
from the pixel-reset level and the signal level. This causes a pipeline effect such that  
the analog output of the first pixel is effectively present at the device output terminal  
at the third rising edge of the X-CLK signal.  
The ADC conversion starts at the falling edge of the CLK-ADC signal and produces a  
valid digital output 20ns after this edge. The timing of these signals is given in  
table 3.  
Table 6: Timing constraints of column read out  
Symbol Min  
Typ  
Description  
a
b
c
40 ns  
40 ns  
0
Address setup time  
Address valid time  
20 ns  
ADC output valid after falling edge of CLK_ADC  
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Page 13 of 24  
STAR-1000  
Datasheet  
4. Pin list  
Table 6 is a list of the pin connections; the following tables group the connections by  
their functionality.  
Figure 3: STAR-1000 pin connections  
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Page 14 of 24  
STAR-1000  
Datasheet  
Table 7: Pin list of the STAR-1000 sensor  
Pin Pin name  
Pin type Pin description  
1
2
3
4
5
6
7
A3  
A4  
A5  
A6  
A7  
A8  
A9  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Digital input.  
Address inputs for row and column addressing.  
A9=LSB, A0=MSB.  
Digital Input. Latch address (A0…A9) to Y-register (0 =  
track, 1 = hold).  
8
LD_Y  
Input  
Digital Input. Latch address (A0…A9) to X-register (0 =  
9
LD_X  
track, 1 = hold).  
10  
11  
12  
VDDA  
GNDD  
GNDA  
Supply  
Ground  
Ground  
Input  
Analog power supply of the imager (typical 5V).  
Digital ground of the imager.  
Analog ground of the imager.  
Digital input. Clock X-register (output valid & stable  
when CLK_X is high).  
13  
CLK_X  
Input  
Digital input (high active). Resets row indicated by Y-  
address (see sensor timing diagram).  
14  
RESET_DS  
RESET_DS can be used for dual-slope integration (see  
FAQ).  
Connect to GND for normal operation.  
Digital supply of the image sensor.  
15  
16  
VDDD  
RESET  
Supply  
Input  
Digital input (high active). Resets row indicated by Y-  
address (see sensor timing diagram).  
Input  
Input  
Input  
Digital input (high active). Control signal for column  
amplifier (see sensor timing diagram).  
Digital input (high active). Control signal for column  
amplifier (see sensor timing diagram).  
Analog input. Biasing of address decoder.  
Connect with 100kΩ to VDDA and decouple with 100  
nF to GND.  
Additional analog inputs. For proper conversion with  
on-chip ADC the input signal must lie within the output  
signal range of the image sensor (approximately +2V to  
+4V).  
17  
18  
S
R
19  
NBIAS_DEC  
20  
21  
A_IN2  
A_IN3  
Input  
Input  
Input  
22  
A_IN1  
23  
24  
A_SEL1  
A_SEL0  
Input  
Input  
Input  
Selection of analog channel: ‘00’ selects image sensor  
(’01’ selects A_IN1; ‘10’ A_IN2 and ‘11’ A_IN3).  
Analog input. Bias of output amplifier (speed/power  
control).  
Connect with 100kΩ to VDDA and decouple with 100  
nF to GND for 12.5 MHz output rate (lower resistor  
values yield higher maximal pixel rates at the cost of  
extra power dissipation).  
25  
NBIAS_OAMP  
Input  
Input  
Analog input. Biasing of the multiplexer circuitry.  
Connect with 20kΩ to GND and decouple with 100nF to  
VDD.  
26  
27  
PBIAS  
G1  
Digital input. Select output amplifier gain value: G0 =  
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Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
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Page 15 of 24  
STAR-1000  
Datasheet  
Pin Pin name  
Pin type Pin description  
Input  
Input  
LSB; G1 = MSB (‘00’ = unity gain; ‘01’ = x2; ‘10’= x4;  
28  
G0  
‘11’=x8).  
Digital input (active high). Initialization of output  
amplifier. Output amplifier will output BLACKREF in  
unity gain mode when CAL is high (1).  
Apply pulse pattern (see sensor timing diagram).  
Analog output video signal.  
29  
CAL  
Output  
Input  
30  
31  
OUT  
To be connected to the analog input of the internal (pin  
52) 10-bit ADC or an external ADC.  
Analog input. Control voltage for output signal offset  
level.  
BLACKREF  
Buffered on-chip, the reference level can be generated by  
a 100kΩ resistive divider. Connect to 2 V DC for use  
with on-chip ADC.  
32  
33  
34  
35  
VDDA  
VDDD  
GNDA  
GNDD  
Supply  
Supply  
Ground  
Ground  
Input  
Analog power supply of image core (typical 5 V).  
Digital power supply of image core (typical 5V).  
Analog ground of image core.  
Digital ground of image core.  
Analog input. Biasing of the pixel array.  
Connect with 1MΩ to VDDA and decouple with 100 nF  
capacitor to GND.  
36  
37  
38  
NBIAS_ARRAY  
TESTPIX_OUT  
TESTPIX_RESET  
Output  
Input  
Output of single test pixel. Can be used for electro-  
optical evaluation.  
Digital input (active high). Reset signal of single test  
pixel. Used to reset the single test pixel during electro-  
optical evaluation.  
39  
40  
41  
42  
43  
44  
45  
46  
47  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
n.c.  
Output  
Output  
Analog output of an array of 20 x 35 test pixels where all  
photodiodes are connected in parallel. Can be used for  
electro-optical evaluation.  
48  
TESTPIXARRAY  
Plain photo diode (without circuitry). Area of the  
photodiode = 20 x 35 pixels. Can be used for electro-  
optical evaluation.  
49  
PHOTODIODE  
50  
51  
NBIAS_ANA  
NBIAS_ANA2  
Input  
Input  
Analog input. Analog biasing of the ADC circuitry.  
Connect with 100kΩ to VDDA and decouple with 100nF  
to GND.  
Input  
Analog input of the internal ADC. Connect to analog  
output of image sensor (pin 30).  
52  
IN_ADC  
Input range (typically 2V and 4V) of the internal ADC is  
set between by VLOW_ADC (pin 55) and  
VHIGH_ADC (pin 62).  
53  
54  
VDD_ADC_ANA Supply  
GND_ADC_ANA Ground  
Analog power supply of the ADC (typical 5V).  
Analog ground of the ADC.  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 16 of 24  
STAR-1000  
Datasheet  
Pin Pin name  
Pin type Pin description  
Input  
Low reference voltage of internal ADC. Nominal input  
range of the ADC is between 2V and 4V. The resistance  
between VLOW_ADC and VHIGH_ADC is about 1.5  
55  
VLOW_ADC  
kΩ.  
Connect with 1k5Ω to GND and decouple with 100nF to  
GND.  
56  
57  
n.c.  
Input  
Input  
Connect with 20K to GND and decouple with 100nF to  
VDDA.  
Digital input. Inversion of the ADC output bits. 0 =  
invert output bits (0 => black: 1023; white: 0), 1 = no  
inversion of output bits (black: 0; white: 1023).  
PBIASDIG2  
58  
59  
BITINVERT  
TRI_ADC  
Input  
Input  
Digital input. Tri-state control of digital ADC outputs (1  
= tri-state; 0 = normal mode).  
ADC output bits.  
60  
61  
D0  
D0 = LSB, D9=MSB.  
Input  
Input  
CLK  
Digital input. ADC clock. ADC converts on falling edge.  
High reference voltage of internal ADC. Nominal input  
range of the ADC is between 2V and 4V. The resistance  
between VLOW_ADC and VHIGH_ADC is about 1.5  
kΩ.  
62  
VHIGH_ADC  
Connect with 1k1Ω to VDDA and decouple with 100nF  
to GND.  
63  
64  
65  
66  
GND_ADC_ANA Ground  
VDD_ADC_ANA Supply  
VDD_ADC_DIG  
GND_ADC_DIG  
Analog ground of the ADC circuitry.  
Analog supply of the ADC circuitry (typical 5V).  
Digital supply of the ADC circuitry (typical 5V).  
Digital ground of the ADC circuitry.  
Power supply of ADC digital output. Connect to 5V for  
or normal operation. Can be brought to lower voltage  
when image sensor must be interfaced to low voltage  
periphery.  
Supply  
Output  
Supply  
67  
VDD_DIG_OUT  
68  
69  
70  
71  
72  
73  
74  
D1  
Output  
Output  
Output  
Output  
Output  
Supply  
Ground  
Supply  
ADC output bits.  
D0 = LSB, D9=MSB.  
D2  
D3  
D4  
D5  
VDDA  
GNDA  
Analog supply of the image core (typical 5V).  
Analog ground of the image core (typical 5V).  
Anti-blooming drain control voltage. Default: connect to  
ground, the anti-blooming is operational but not  
maximal. Apply 1 V DC for improved anti-blooming.  
Analog supply. Reset level for RESET_DS. Can be used  
for extended optical dynamic range. See FAQ for more  
details.  
75  
GND_AB  
Supply  
76  
VREF  
77  
78  
79  
80  
81  
VRES  
D6  
Supply  
Output  
Output  
Output  
Output  
Analog supply. Reset level for RESET (typical 5V).  
ADC output bits.  
D0 = LSB, D9=MSB.  
D7  
D8  
D9  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 17 of 24  
STAR-1000  
Datasheet  
Pin Pin name  
Pin type Pin description  
82  
83  
84  
A0  
A1  
A2  
Input  
Input  
Input  
Digital input.  
Address inputs for row and column addressing.  
A9=LSB, A0=MSB.  
Notes:  
1. All pins with the same name can be connected together.  
2. Unused inputs must always be tied to an appropriate level, e.g. VDD or GND.  
3. Note on power up behaviour:  
At power-on, the image sensor is in an undefined state. It is advised that after  
start-up an address is latched ASAP into the Y-decoder and the X-decoder to  
prevent high current consumption.  
4. There’s no on-chip power supply rejection whatsoever. This means that every  
noise signal on the analog supply voltages is copied directly to the analog  
video signal (decoupling of the supply voltages as close as possible to the  
image sensor is recommended).  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 18 of 24  
STAR-1000  
Datasheet  
5. Packaging and Geometrical constraints  
5.1.  
Package drawing  
The detector is packaged in an 84-pin J-leaded package.  
The detector is mounted into position with thermally and electrically conductive  
adhesive. The bottom plate of the cavity will be electrically connected to a ground  
pin.  
The detector will be positioned into the cavity such that the optical centre of the  
detector coincides with the geometrical centre of the cavity within a tolerance of  
± 50 µm in X- and Y direction. The tolerance on the parallelism of the detector is  
± 50 µm in X- and Y-direction.  
Figure 4: Package drawing  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 19 of 24  
STAR-1000  
Datasheet  
5.2.  
Die alignment  
Parallelism in  
X and Y within  
± 50  
µm  
200 u  
Center of  
Cavity and  
of FPA  
Y
Pin 1  
A
X
Center of  
Silicium  
Offset between center of  
silicium and center of cavity:  
X = - 52 µm  
A
Y = - 200 µm  
52 u  
0.508  
±0.051  
Bonding  
cavity  
0.508  
±0.01  
Die:  
Glass window:  
1.0 +/- 0.05  
Window  
adhesive:  
0.08 ±0.02  
Die  
cavity:  
0.508  
±0.051  
Die adhesive  
0.08 ±0.02  
Section  
A
-A  
Drawing not to scale  
Figure 5: Die alignment  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 20 of 24  
STAR-1000  
Datasheet  
6. Ordering Information  
FillFactory Part Number  
STAR-1000  
Cypress Semiconductor Part Number  
CYIS1SM1000AA-HFC - (Preliminary)  
Disclaimer  
FillFactory image sensors are only warranted to meet the specifications as described  
in the production data sheet. FillFactory reserves the right to change any information  
contained herein without notice.  
Please contact info@FillFactory.com for more information.  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 21 of 24  
STAR-1000  
Datasheet  
APPENDIX A: STAR-1000 evaluation system  
For evaluating purposes an STAR-1000 evaluation kit is available.  
The STAR-1000 evaluation kit consists of a multifunctional digital board (memory,  
sequencer and IEEE 1394 Fire Wire interface) and an analog image sensor board.  
Visual Basic software (under Win 2000 or XP) allows the grabbing and display of  
images from the sensor. All acquired images can be stored in different file formats (8  
or 16-bit). All setting can be adjusted on the fly to evaluate the sensors specs. Default  
register values can be loaded to start the software in a desired state.  
Please contact Fillfactory (info@Fillfactory.com) if you want any more information  
on the evaluation kit.  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 22 of 24  
STAR-1000  
Datasheet  
APPENDIX B: Frequently Asked Questions  
Q:  
How does the dual slope extended dynamic range mode works?  
A:  
Dual slope is a method to extend the dynamic range of a normally linear-  
transfer imager, by combining the images taken with a long integration time  
(dark areas of a scene) and a short integration time (bright areas of a scene)  
into one image and this in one integration time cycle i.e. without combining  
two different images. The resulting electro-optical transfer curve is bi-linear.  
Please look at our website to find some pictures with extended dynamic range:  
http://www.fillfactory.be/htm/technology/htm/dual-slope.htm.  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 23 of 24  
STAR-1000  
Datasheet  
Document History Page  
Document Title:  
STAR-1000 1M Pixel Radiation Hard CMOS Image Sensor  
Document Number: 38-05714  
Rev.  
ECN  
Issue Date  
Orig. of  
Change  
SIL  
Description  
of Change  
Initial  
No.  
**  
310213  
See ECN  
Cypress  
release  
EOD  
Cypress Semiconductor Corporation 3901 North First Street  
Contact: info@Fillfactory.com Document #:38-05714 Rev.**(Revision 6.5)  
San Jose, CA 95134 408-943-2600  
Page 24 of 24  
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