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IXS839BD2

型号：

IXS839BD2

品牌：

LITTELFUSE[ LITTELFUSE ]

页数：

13 页

PDF大小：

394 K

下载PDF手册
IXYS  
IXS839 / IXS839A / IXS839B  
Synchronous Buck MOSFET Driver  
Features:  
General Description  
The IXS839/IXS839A/IXS839B are 2A Source / 4A  
Sink Synchronous Buck MOSFET Drivers. These  
Synchronous Buck MOSFET Drivers are specifically  
designed to drive two N-channel power MOSFETs  
in a synchronous buck converter. The High-Side  
driver is powered via a bootstrapped power  
connection. The driver is capable of 20ns High-Side  
output, and 18ns Low-Side output transition times  
driving a 3000pF load.  
• Logic Level Gate Drive Compatible  
• 2A Source, 4A Sink Peak Drive Current  
• Programmable High-Side Driver Turn-on Delay  
• Supports Floating Voltage for Top Driver Up to  
24V  
• IXS839/839B: Undervoltage Lockout  
• IXS839A/B: Output Shutdown, Low Side  
Shutdown Inputs  
The IXS839 and IXS839B incorporate an  
undervoltage lockout to prevent unintentional gate  
drive output during low voltage conditions. The  
IXS83A/B include External Shutdown and Low-Side  
Drive Shutdown features. Simultaneous shutdown  
of both outputs prevents rapid output capacitor  
discharge. The high-side turn-on delay is adjustable  
with an external capacitor added at the DLY pin.  
• 10µA Shut Down Current  
• 2mA Quiescent Current (Non- Switching)  
• Bootstrapped High Side Driver  
• Cross-Conduction Protection  
Applications:  
• Multiphase Desktop CPU Supplies  
• Mobile CPU Core Voltage supplies  
The IXS839/839A/839B are designed to operate  
over a temperature range of -40°C to +85°C. The  
IXS839 is available in an 8-Lead SOIC, the  
IXS839A and the IXS839B in a 10-pin QFN.  
• High Current / Low Voltage DC/DC  
Synchronous Buck Converters  
Figure 1. IXS839 Functional Block Diagram  
and General Application Circuit  
Figure 2. IXS839A Functional Block Diagram  
and General Application Circuit  
5V  
VDD  
VIN  
5V  
VDD  
VIN  
8
4
DBST  
DBST  
BST  
HGD  
SW  
UVLO  
BST  
HGD  
SW  
3
2
1
8
Q1  
SD  
Q1  
4
5
PWM  
OVERLAP  
PROTECTION  
CIRCUIT  
OVERLAP  
PROTECTION  
CIRCUIT  
2
3
CBST  
CBST  
PWM  
1
7
VOUT  
VOUT  
DLY  
DLY  
7
LGD  
LGD  
Q2  
Q2  
9
5
6
CDLY  
CDLY  
PGND  
PGND  
10  
6
LSD  
Copyright © IXYS CORPORATION 2005  
9/9/2005  
IXS839 / IXS839A / IXS839B  
IXYS  
Figure 3. IXS839B Functional Block Diagram and General Application Circuit  
5V  
VDD  
VIN  
5
DBST  
UVLO  
BST  
HGD  
SW  
10  
9
Q1  
SD  
1
2
OVERLAP  
PROTECTION  
CIRCUIT  
CBST  
PWM  
8
VOUT  
DLY  
4
3
LGD  
Q2  
6
7
CDLY  
PGND  
LSD  
Ordering Information  
Part No.  
Description  
Package  
Pack Quantity  
Under Voltage Lockout  
Under Voltage Lockout  
Under Voltage Lockout  
IXS839S1  
IXS839S1T/R  
IXS839D1  
8-Pin SOIC 98 (Tube)  
8-Pin SOIC 2500 (Tape & Reel)  
Tested Die  
Driver Shutdown, Low Side Shutdown  
Driver Shutdown, Low Side Shutdown  
Driver Shutdown, Low Side Shutdown  
IXS839AQ2  
IXS839AQ2T/R  
IXS839AD2  
IXS839BQ2  
IXS839BQ2T/R  
IXS839BD2  
10-Pin QFN 121 (Tube)  
10-Pin QFN 2000 (Tape & Reel)  
Tested Die  
10-Pin QFN 121 (Tube)  
10-Pin QFN 2000 (Tape & Reel)  
Tested Die  
Under Voltage Lockout , Driver Shutdown, Low Side Shutdown  
Under Voltage Lockout , Driver Shutdown, Low Side Shutdown  
Under Voltage Lockout , Driver Shutdown, Low Side Shutdown  
Absolute Maximum Ratings  
Parameter  
VDD  
Rating  
Absolute Maximum Ratings are stress ratings.  
Stresses in excess of these ratings can cause  
permanent damage to the device. Functional  
operation of the device at these or any other  
conditions beyond those indicated in the operational  
sections of this data sheet is not implied. Exposure  
of the device to the absolute maximum ratings for  
an extended period may degrade the device and  
affect its reliability.  
-0.3V to +7V  
-0.3V to +30V  
-0.3V to +7V  
-0.2V to +24V  
-0.3V to +7V  
-40°C to +85°C  
-40°C to +125°C  
150°C/W  
BST  
BST to SW  
SW  
PWM  
Operating Ambient Temp Range  
Operating Junction Temp Range  
θJA  
θJC  
40°C/W  
Storage Temp Range  
-65°C to +150°C  
Lead Temperature (Soldering, 10 sec) +300°C  
ESD Warning  
ESD (electrostatic discharge) sensitive device. Electrostatic charges can readily accumulate on test equipment and the human body  
in excess of 4000 Volts. This energy can discharge without detection. Although the IXS839/839A/839B feature proprietary ESD  
protection circuitry, permanent damage may be sustained if subjected to high energy electrostatic discharges. Proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
2
IXS839 / IXS839A / IXS839B  
IXYS  
Pin Description and Configurations  
IXS839 IXS839A IXS839B  
Name  
Description  
Upper Gate Driver Floating DC Power Terminal for Bootstrap  
Capacitor Connection.  
1
2
3
5
10  
2
BST  
TTL-level Input Signal with active pull-down. PWM input to the  
Gate Drivers.  
PWM  
DLY  
Terminal for External Delay Capacitor Connection. Capacitor  
to Ground at this pin adds propagation delay from Lower Gate  
Driver going Low to the Upper Gate Driver going High.  
3
4
7
8
4
5
t
DLY (nS) = CDLY (pF) x (0.5nS/pF)  
Positive Supply Terminal for Logic and Lower Gate Driver. A  
ceramic bypass capacitor of 1uF should be connected from  
VDD to PGND.  
VDD  
Lower Gate Driver Output Terminal  
5
6
7
8
9
10  
1
6
7
8
9
LGD  
PGND  
SW  
Lower Gate Driver DC Power Return Terminal, Logic and  
Analog Ground  
Upper Gate Driver Floating DC Power Return Terminal  
Upper Gate Driver Output Terminal  
2
HGD  
__  
SD  
TTL-level Shut Down Input Signal with active pull-up.  
SD enables normal operation when high. When SD is low,  
the driver outputs are forced low and IDD is at its minimum.  
N/A  
N/A  
4
6
1
3
___  
LSD  
TTL-level Low Side Shut Down Input Signal with active pull-  
up. LSD, when low forces the Lower Gate Driver output low.  
When LSD is high, the lower Gate Driver output is enabled.  
SOIC and QFN Top View Pin Configurations  
SW  
1
PGND  
LGD  
10  
9
SD  
1
2
10 BST  
8
7
HGD  
SW  
BST 1  
PWM 2  
DLY 3  
VDD 4  
PWM  
HGD  
BST  
HGD  
9
IXS839BQ2  
2
IXS839AQ2  
IXS839S1  
8
8
SW  
3
4
5
3
4
5
VDD  
DLY  
LSD  
DLY  
PGND  
LGD  
6
5
PGND  
SD  
7
6
7
6
PWM  
LGD  
LSD  
VDD  
3
IXS839 / IXS839A / IXS839B  
IXYS  
Electrical Characteristics  
Power Supply Terminals  
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V  
Parameter  
Symbol  
Conditions  
Min Typ Max Unit  
Analog Supply  
Voltage Range  
High Gate Driver  
Supply Voltage Range  
Low Gate Driver  
Supply Voltage Range  
Floating Supply  
Voltage Range  
Analog Supply  
Current  
VDD  
VDD  
4.5  
4.5  
4.5  
0.0  
5.5  
5.5  
5.5  
24.0  
4
V
V
VBST - VSW  
VDD - VPGND  
VSW - VPGDN  
V
V
Normal Mode  
PWM = VPGND  
IDD  
2
mA  
mA  
IXS839/839B  
IXS839A  
0.5  
1
1.5  
High Gate Driver  
Supply Current  
Normal Mode  
PWM = VPGND  
IBST  
IXS839/839B  
IXS839A  
10  
50  
Analog Supply  
Current  
Shut Down Mode, LSD = VDD,  
SD = PWM = VPGND  
IDD_Shutdown  
IBST_Shutdown  
µA  
µA  
High Gate Driver  
Supply Current  
Shut Down Mode  
LSD = PWM = VPGND  
<1  
10  
Digital Input Terminals  
Parameter  
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
PWM = VPGND  
LSD = SD = VDD  
Input Leakage Current  
IIN  
-1  
1
µA  
Input pull-down Current  
PWM = VDD  
2
10  
100  
µA  
µA  
__  
Input pull-up Current  
Input pull-up Current  
-2  
-10  
-100  
SD = VPGND  
___  
LSD = VPGND  
-2  
-10  
-100  
µA  
Minimum High Level  
Input Voltage  
Maximum Low Level  
Input Voltage  
VIH  
VIL  
2.0  
V
V
0.8  
UVLO Circuit  
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V  
Parameter  
VDD Rising Threshold  
VDD Falling Threshold  
Symbol  
UVOLRISE  
UVOLFALL  
Conditions  
Min  
4.2  
3.9  
Typ  
4.4  
4.25  
Max  
4.5  
4.5  
Unit  
V
V
Delay Circuit  
Parameter  
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Upper Gate-Driver Turn  
on Delay Time with  
respect to external delay  
capacitor  
Capacitor CDLY(pF) from DLY  
pin to PGND  
tDLY  
0.5  
nS/pF  
4
IXS839 / IXS839A / IXS839B  
IXYS  
Electrical Characteristics  
High Side Gate Driver Circuit  
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
High Side Gate-Driver  
On-Resistance, Sourcing RHGD_SRC  
Current  
VBST – VSW = 4.6V  
2.2  
Ω
High Side Gate-Driver  
On-Resistance, Sinking  
Current  
RHGD_SNK  
VBST – VSW = 4.6V  
1.2  
20  
15  
Ω
CLOAD = 3nF  
TR_HGD measured from 10% to  
90% of (VHGD - VSW  
CLOAD = 3nF  
TF_HGD measured from 90% to  
10% of (VHGD - VSW  
High Side Gate-Driver(1)  
Rise-Time  
tR_HGD  
nS  
nS  
)
High Side Gate-Driver(1)  
Fall-Time  
tF_HGD  
)
35  
50  
nS  
nS  
tPD_HGD1  
tPD_HGD2  
CLOAD_HGD = CLOAD_LGD = 3nF  
CDLY = 0pF  
Propagation Delay(1)  
Low Side Gate Driver Circuit  
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Low Side Gate-Driver  
On-Resistance, Sourcing RLGD_SRC  
Current  
VDD – VPGND = 4.6V  
2
Ω
Low Side Gate-Driver  
On-Resistance, Sinking  
Current  
RLGD_SNK  
VDD – VPGND = 4.6V  
CLOAD = 3nF  
1
Ω
Low Side Gate-Driver(1)  
Rise-Time  
tR_LGD  
T
R_LGD measured from 10% to  
18  
12  
nS  
nS  
90% of (VLGD – VPGND  
CLOAD = 3nF  
)
Low Side Gate-Driver(1)  
Fall-Time  
tF_LGD  
T
F_LGD measured from 90% to  
10% of (VLGD - VSW  
CLOAD_HGD = CLOAD_LGD = 3nF  
DLY = 0pF  
)
60  
20  
nS  
nS  
tPD_LGD1  
tPD_LGD2  
Propagation Delay(1)  
C
Shut Down Circuit Characteristics  
TA = -40°C to 85°C, VDD = 5V, 4V < VBST < 26V  
Parameter  
Symbol  
tPD_LGDSD1  
tPD_LGDSD2  
tPD_GDSD1  
tPD_GDSD2  
Conditions  
Min  
Typ  
25  
10  
400  
800  
Max  
50  
20  
800  
1200  
Unit  
nS  
nS  
nS  
nS  
Propagation Delay(2)  
Propagation Delay(2)  
Propagation Delay(3)  
Propagation Delay(3)  
*Notes:  
(1) See Timing Diagram in Figure 4  
(2) See Timing Diagram in Figure 5  
(3) See Timing Diagram in Figure 6  
5
IXS839 / IXS839A / IXS839B  
IXYS  
Figure 4. Non-Overlap Timing Diagram for IXS839/839A/839B  
PWM  
tpd_lgd2  
LGD  
tpd_hgd2  
tf_lgd  
10%  
tr_lgd  
90%  
tpd_lgd1  
tr_hgd  
90%  
tf_hgd  
tpd_hgd1  
HGD-SW  
10%  
___  
__  
Figure 5. LSD Propagation Delay Timing  
for IXS839A/B  
Figure 6. SD Propagation Delay Timing  
for IXS839A/B  
LSD  
10%  
SD  
10%  
tpd_lgdsd2  
tpd_gdsd2  
tpd_lgdsd1  
LGD  
tpd_gdsd1  
LGD/HGD  
90%  
90%  
6
IXS839 / IXS839A / IXS839B  
IXYS  
IXS839 and IXS839B Die Size and Pad Locations:  
Passivation Opening  
Location (1)  
X (um)  
Ref. No.  
Signal Name  
HGD  
HGD  
SW  
Signal Type  
X (um)  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
100  
100  
Y (um)  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
100  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
100  
100  
Y (um)  
266  
412  
598  
744  
968  
1461  
1608  
1644  
1644  
1644  
1644  
1464  
1237  
899  
672  
477  
280  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
0
1
2
3
4
5
6
7
8
Digital Output  
Digital Output  
Power Supply  
Power Supply  
Power Supply  
Power Supply  
Power Supply  
Digital Output  
Digital Output  
Power Supply  
Power Supply  
2
2
2
2
0
2
2
SW  
VSS  
PGND  
PGND  
LGD  
LGD  
VDD  
VDD  
590  
737  
903  
1050  
1283  
1283  
1283  
1283  
1283  
1283  
N/A  
N/A  
N/A  
N/A  
N/A  
N/A  
337  
190  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
PRDY (Power Ready) Digital Output  
DLY  
SMOD (LSD BAR)  
PWM  
VSS  
SD (SDI BAR)  
VBG  
TST  
T0  
T1  
Digital I/O  
Digital Input  
Digital Input  
Power Supply  
Digital Input  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
No Connect  
Power Supply  
Power Supply  
T2  
TGND  
BST  
BST  
0
Notes:  
(1) Location is the distance from origin to the center of the passivation opening.  
7
IXS839 / IXS839A / IXS839B  
IXYS  
IXS839A Die Size and Pad Locations:  
Passivation Opening  
Location (1)  
X (um)  
0
56  
534  
673  
953  
936  
940  
893  
508  
282  
57  
Ref. No.  
Signal Name  
HGD  
SW  
VSS  
PGND  
PGND  
LGD  
VDD  
DLY  
SMOD (LSD BAR)  
PWM  
PDB (SDI BAR)  
BST  
Signal Type  
X (um)  
81  
190  
81  
Y (um)  
190  
81  
Y (um)  
598  
1211  
1268  
1268  
1083  
586  
243  
18  
0
0
7
307  
1
2
3
4
5
6
7
8
9
Digital Output  
Power Supply  
Power Supply  
Power Supply  
Power Supply  
Digital Output  
Power Supply  
Digital I/O  
Digital Input  
Digital Input  
Digital Input  
Power Supply  
81  
81  
81  
81  
81  
81  
81  
190  
190  
100  
115  
115  
100  
190  
100  
100  
100  
100  
81  
10  
11  
12  
0
Notes:  
(1) Location is the distance from origin to the center of the passivation opening.  
8
IXS839 / IXS839A / IXS839B  
IXYS  
Typical Performance Characteristics  
Fig 7. HGD Fall and LGD Rise Times  
Fig 8. LGD Fall and HGD Rise Times  
25  
20  
25  
20  
15  
15  
HGD  
HGD  
10  
5
0
10  
LGD  
LGD  
5
Vdd=5V  
Vdd=5V  
Cl=3nF  
Cl=3nF  
0
-40  
-15  
10  
35  
60 85  
-40  
-15  
10  
35  
Ta (°C)  
60 85  
Ta (°C)  
Fig 9. HGD & LGD Rise Time vs. Temperature  
Fig 10. HGD & LGD Fall Time vs. Temperature  
25  
20  
25  
20  
HGD  
15  
15  
HGD  
10  
10  
LGD  
LGD  
5
5
Vdd=5V  
Ta=25C  
Vdd=5V  
Ta=25C  
0
0
1.0  
1.0  
2.0  
3.0  
4.0  
5.0  
2.0  
3.0  
Capacitance (nF)  
4.0 5.0  
Capacitance (nF)  
Fig 11. HGD and LGD Rise Time vs. Load Capacitance  
Fig 12. HGD and LGD Fall Time vs. Load Capacitance  
9
IXS839 / IXS839A / IXS839B  
IXYS  
Typical Performance Characteristics  
50  
50  
40  
40  
30  
20  
10  
0
Tpd_lgd1  
Tpd_hgd2  
30  
20  
10  
0
Tpd_hgd1  
Vdd=5V  
Cl=3nF  
Vdd=5V  
Cl=3nF  
Tpd_lgd2  
-40  
-15  
10  
35  
60  
85  
-40  
-15  
10  
35  
60  
85  
Ta (°C)  
Ta (°C)  
Fig 13. HGD Propagation Delay vs. Temperature  
Fig 14. LGD Propagation Delay vs. Temperature  
120  
90  
20  
15  
60  
10  
Vdd=5V  
Ta=25C  
30  
5
250kHz  
Vdd=5V  
Cl=3nF  
Cl=3nF  
0
0
-40  
-15  
10  
35  
60 85  
0
500  
1000 1500 2000  
Frequency (kHz)  
Ta (°C)  
Fig 15. Supply Current vs. Frequency  
Fig 16. Supply Current vs. Temperature  
10  
IXS839 / IXS839A / IXS839B  
IXYS  
Package Outlines  
8-PIN SOIC  
QFN - 10  
(REF.)  
TOP VIEW  
SIDE VIEW  
11  
IXS839 / IXS839A / IXS839B  
IXYS  
Low-Side Gate Driver  
Theory of Operation  
The Low-Side Gate Driver is designed to drive a  
ground referenced N-Channel Power MOSFET. In  
a synchronous buck converter application, it drives  
the gate of the synchronous rectifier FET, (Q2).  
When the driver is enabled, (IXS839A/B  
SD=LSD=VDD), the driver output is 180˚ out of  
phase with the PWM input. The internal overlap  
protection circuit monitors the High-Side Gate  
Driver, and allows the Low-Side Gate Driver to turn  
on only when the High-Side Gate Driver output falls  
below 1.0 Volt. The supply rails for the Low-Side  
Gate Driver are VDD and PGND.  
The IXS839/839A/839B are dual MOSFET drivers,  
designed to drive two external N-channel power  
MOSFETs. The low-side driver is designed to drive  
a non-floating N-channel power MOSFET and its  
output is out of phase with the PWM input. The  
high-side driver is designed to drive a floating N-  
channel power MOSFET and its output is in phase  
with the PWM input. An external bootstrap circuit  
provides the floating power supply to the high-side  
driver.  
The bootstrap circuit consists of a Schottky diode  
and a boost capacitor. When the PWM input  
transitions to a logic low, the low-side power  
MOSFET turns ON, the SW node is pulled to  
ground, and the bootstrap capacitor is charged to  
VDD through the Schottky diode. When the PWM  
transitions to a logic high, the high side power  
MOSFET begins to turn on and the SW node rises  
up to the input supply, VIN. In turn the boost  
capacitor raises the BST node voltage to a level  
equal to the input supply plus the boost capacitor  
voltage, providing sufficient voltage to the BST  
node to turn on the High-Side Power MOSFET. An  
High-Side Gate Driver  
The High-Side Gate Driver is designed to drive a  
floating N-Channel Power MOSFET referenced to  
SW. In a synchronous buck converter application, it  
drives the gate of the high side power MOSFET,  
(Q1). When the driver is enabled (IXS839A/B  
SD=VDD), the driver output is in phase with the  
PWM input. The bootstrap supply rails for the High-  
Side Gate Driver are BST and SW, and are  
generated by an external bootstrap circuit. The  
bootstrap circuit consists of a Schottky diode  
DBST, and a bootstrap capacitor CBST. During  
start up, the SW pin is at ground and the bootstrap  
capacitor CBST charges up to VDD through the  
Schottky diode DBST. When the PWM input  
transitions high the High-Side Gate Driver begins to  
turn Q1 ON by transferring charge from the  
bootstrap capacitor CBST to the gate of Q1. As Q1  
turns on the SW pin will rise up to VIN, forcing the  
BST pin to VIN + VBOOSTCAP. This supplies the  
required gate to source voltage to Q1. When PWM  
transitions low the High-Side Driver and in turn Q1  
switch off. When SW falls below 1 Volt the Low-  
Side Gate Driver turns on and recharges the  
bootstrap capacitor which completes the cycle.  
internal  
cross-conduction  
prevention  
circuit  
monitors both gate driver outputs and allows each  
driver output to turn ON only when the other output  
driver turns OFF and falls below 1V.  
The IXS839A is  
a
cost reduced Driver,  
differentiated by the absence of the undervoltage  
lockout protection circuit featured in the IXS839 and  
IXS839B. IXS839A/B must be enabled using the  
SD terminal when the driver supply reaches the  
operating range. SD can be used to turn off both  
driver outputs to prevent the rapid discharge of the  
buck converter output capacitors. An additional  
terminal, LSD can be used to turn off the Low-Side  
Gate Driver Output. The High-Side Gate Driver  
remains active in this mode.  
Overlap Protection Circuit  
The overlap protection circuit (OPC) monitors the  
High Side and Low Side Gate Driver Outputs and  
prevents both main power switches, Q1 and Q2,  
from being ON at the same time. This inhibits  
excessive shoot-through currents and minimizes  
the associated losses.  
Detailed Circuit Description  
(Refer to the Application Diagrams)  
The PMW input signal controls both the High Side  
and Low Side power MOSFET drivers. The Power  
MOSFETs are driven so that the SW node follows  
the polarity of the PWM signal.  
When the PWM input transitions low, Q1 begins to  
turn OFF, and Q2 turns ON only when the High-  
Side Gate Driver output falls below 1 volt. By  
12  
IXS839 / IXS839A / IXS839B  
IXYS  
waiting for the voltage on the High Side Gate  
Driver Output pin to reach 1 volt, the overlap  
protection circuit ensures that Q1 is OFF before Q2  
turns on.  
Application Information  
Supply Capacitor Selection  
A 1 uF ceramic bypass capacitor is recommended  
for the VDD input to provide noise suppression.  
The bypass capacitor should be located as close  
as possible to the IXS939/A/B.  
Similarly, when the PWM input transitions high, Q2  
begins to turn OFF, and Q1 turns ON after the  
overlap protection circuit detects that the voltage at  
the Low-Side Gate Driver output has dropped  
below 1 volt. Once the driver output voltage falls  
below 1 volt, the overlap protection circuit initiates  
a delay timer that adds additional delay set by the  
external capacitor connected to the DLY pin. This  
programmable delay circuit allows adjustments to  
optimize performance based on the switching  
characteristics of the external power MOSFET.  
Bootstrap Circuit  
The bootstrap circuit requires a charge storage  
capacitor CBST and a Schottky diode DBST, as  
shown in Figure 1. Selecting these components  
should be done with consideration of the electrical  
characteristics of the high-side FET chosen.  
The bootstrap capacitor voltage rating must  
exceed the maximum input voltage, (VIN) + the  
maximum VDD voltage. The capacitance is  
determined using the following equation:  
QGATE  
Low-Side Driver Shutdown  
The IXS839A/B include a Low-Side Gate Driver  
shutdown feature. A logic low signal at the LSD  
input shuts down the Low Side Gate Driver, and in  
turn the synchronous rectifier FET. This signal can  
be used to achieve maximum battery life under  
light load conditions and maximum efficiency under  
heavy load conditions. Under heavy load  
conditions, LSD should be high so that the  
synchronous switch is controlled by the PWM  
signal for maximum efficiency. Under light load  
conditions the LSD can be low to disable the Low  
Side Gate Driver so the switching current can be  
minimized.  
CBST  
=
∆VBST  
Where, QGATE is the total gate charge of Q1, and  
∆VBST is the allowable Q1 voltage droop.  
To maximize the available drive for Q1 in the  
bootstrap circuit a Schottky diode is recommended.  
The bootstrap diode voltage rating must exceed  
the maximum input voltage, (VIN) + the maximum  
VDD voltage. The average forward current can be  
estimated by:  
IF(AVG) = QGATE X FMAX  
where FMAX is the maximum PWM input switching  
frequency. Peak surge current is dependent on the  
source impedance of the 5V supply and the ESR  
of CBST, and should be checked in-circuit.  
Shutdown  
For optimal system power management, the  
IXS839A/B drivers can be shut down to conserve  
power. When the SD pin is high, the IXS839A/B  
are enabled for normal operation. Pulling the SD  
pin low forces the HGD and LGD outputs low, and  
reduces the supply current by disabling the internal  
reference.  
Delay Capacitor Selection  
A ceramic capacitor is recommended for the DLY  
input, and should be located as close a possible to  
the DLY pin.  
Under Voltage Lockout (IXS839 and IXS839B)  
The Under Voltage Lockout (UVLO) circuit holds  
both driver outputs low during VDD supply ramp-  
up. The UVLO logic becomes active and in control  
of the driver outputs at a supply voltage of no  
greater than 1.5 V. When the supply voltage rises  
above the UVLO upper threshold the circuit allows  
the PWM input to control the drivers.  
Printed Circuit Board Layout Considerations  
Use the following general guidelines when  
designing printed circuit boards:  
1. Trace out the high current paths and use short,  
wide traces to make these connections.  
2. Locate the VDD bypass capacitor as close as  
possible to the VDD and PGND pins.  
3. Connect the source of the Lower MOSFET,  
(Q2) as close as possible the PGND.  
13  
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