IXD5118
BASIC OPERATION
Operation of the IXD5118 in a typical application circuit is exlained by the timing diagram shown below.
Å At initial state, the sufficiently high voltage (6.0 V MAX.) applies to the sense pin, and the delay capacitor CD is
charged to the power supply input voltage (1.0V ≤ VIN ≤ 6.0 V). While the sense pin voltage (VSEN) starts
dropping, the output voltage VOUT remains at “High” level equal VIN as long, as the detect voltage VSEN > VDF
.
(Output voltage “High” level is equal pull-up voltage for IXD518N version.)
Ç The sense pin voltage keeps dropping and becomes equal to the detect voltage (VSEN =VDF), Comparator (see
Block Diagram) trips, a N-channel transistor M1 turns ON, discharging the delay capacitor CD, and the output
voltage changes state to the “Low” level, equal VSS.
The detect delay time tDF is defined as time from the moment, when VSEN = VDF to the moment, when VOUT
changes state to “Low” level (tDF0, when the CD pin is open).
É The output voltage maintains at the “Low” level as long as the sense pin voltage is below the release voltage
(VSEN< VDF +VHYS), and the delay capacitor CD remains discharged to the ground voltage level.
Ñ When the sense pin voltage increases to the release voltage level (VSEN = VDF + VHYS), the N-channel transistor
M1 turns OFF, and the delay capacitor CD start charging via a delay resistor RDEL
.
Ö The CD pin voltage (VCD) continues rising up to the CD pin threshold voltage (VTCD), because the sense pin
voltage is higher than the release voltage.
The time constant of the CD pin voltage is τ = RDELCD, so the Release Delay Time (tDR) can be determined as
tDR = -RDEL × CD × ln(1-VTCD/VIN) …(1)
The Release Delay time can also be calculated with the formula (2), because RDEL = 2.0 MΩ (TYP.) and the
delay CD pin threshold voltage is VIN /2 (TYP.)
tDR = RDEL × CD × 0.69 …(2)
As an example, presuming that the delay capacitance is 0.68 µF, tDR is :
tDR =2.0 ×106×0.68 ×10-6×0.69 = 938 (ms)
Note that the release delay time may be remarkably short, if the delay capacitor CD did not discharge to the
ground (VSS) level, because of short time in state É.
Ü When the CD pin voltage reaches threshold level (VCD = VTCD), the inverter will change state of the output. As a
result, the output voltage changes into the “High” (VIN) state.
á While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitor charges up to the
input voltage level. The output voltage maintains the “High” level equal VIN.
© 2014 IXYS Corp.
Characteristics subject to change without notice
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Doc. No. IXD5118_DS, Rev. N0
