IDT5T40166
GIGABIT ETHERNET CLOCK GENERATOR
CLOCK SYNTHESIZER
Application Information
Decoupling Capacitors
External Components
As with any high-performance mixed-signal IC, the
IDT5T40166 must be isolated from system power supply
noise to perform optimally.
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01 μF and 0.1
pF should be connected between VDD and GND as close to
the device as possible.
Decoupling capacitors of 0.01 µF and 0.1 pF must be
connected between each VDD and the PCB ground plane.
On chip capacitors- Crystal capacitors is integrated to
support 8 pF crystal load. Crystal should be connected as
close to pins XTALIN and XTALOUT to optimize the initial
accuracy.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01 µF and 0.1 pF decoupling capacitor should be
mounted on the component side of the board as close to the
VDD pin as possible. No vias should be used between
decoupling capacitor and VDD pin. The PCB trace to VDD
pin should be kept as short as possible, as should the PCB
trace to the ground via. Distance of the ferrite bead and bulk
decoupling from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the IDT5T40166.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
LVPECL Test Condition
R
= 50Ohm, C
= 2pF
LOAD
LOAD
IDT® GIGABIT ETHERNET CLOCK GENERATOR
3
IDT5T40166 REV A 082410
