IXHQ 100PI
IXHQ 100SI
the external load, Vload, is zero. As VSLOPE rises,
its rate of increase determined by the value of
the external capacitor, C8 (figure1), and the
value of the internal current source, I5. VGATE's
rateofincreasefollowsVSLOPE. AssoonasVGATE
exceeds VthQ1 (figure 1) of the external power
MOSFET, drain current IdQ1 starts to flow. The
rateofincreaseofIdQ1 isproportionaltotherate
of increase of VSLOPE, and is independent of the
size of C5 , the total filter capacitance of the
load. Note that this rate, which is directly
proportionaltoC7and inversely proportionalto
C8, couldbeadjusted.Similarly theToff-delay
can be adjusted and is directly proportional to
the size of C7.
DEVICE OPERATION*
A hot swap operation involves removal and
reinsertion of a device while the system using
it remains in operation. Such an operation
could cause external capacitors to draw cur-
rentshighenoughtodisturbsystemoperations
or even cause permanent damage to both the
deviceandthesystem.
TheIXHQ100isdesignedtopreventanydistur-
bances or damage during such occurrences,
allowing the circuit board to be safely inserted
andremovedfromalivebackplane. Capableof
operatingunderthreemodes,thechipalsoacts
asapoweractivenoisefilterandanauto-detect
circuit.
Normal Operation
With continuous –Vin applied, the IXHQ100
acts as an active power filter by modulating the
voltage drop across the external Power
MOSFET Vds so that any noise on –Vin is
cancelled by Vds.
The direct connection of IXHQ 100’s AGND pin
to–Vin allowstheVdrop (internallysetto~750mV)
to set the ~90% of the maximum peak noise
voltage reject by the IXHQ100. The internal
Vdrop setting of ~750 mV allows 1.35 Vpp of
noiserejection. Graphonpage5 illustratesthe
level of ripple attenuation during normal
conditions.Noticethatthenoiserejectionisvery
high(~60db)between400Hzto40KHz,whichis
optimal for most hot swap applications.
Insertion Process
As the circuit board is inserted into the
backplane, physical connections should be
made to ground to discharge any electrostatic
voltage. The insertion process begins when
power and ground are supplied to the board
through pins on the blackplane.
Once power is applied, the IXHQ100 starts up
but does not immediately apply power to the
output load. The internal Power Up Reset logic
(see in Figure 2) turns on for 10 µs prior to any
other logic. This pulse goes through two NOR
gatesandresetsSRFF1FlipFlop. OnceSRFF1
is reset, the current source, I6, charges the
OFFTM pin at a rate proportional to the size of
theexternalcapacitor,C7(fig1).Duringthetime
theOFFTMpinisrampingfrom0VtoVrf(~5V),
which is the Toff-delay, COMP1 keeps N3 ON so
VSLOPE stays at 0V. After Toff-delay, VOFFTMecomes
greater than Vrf, and COMP1 goes low, driving
N3 to off state. I5 now starts to charge C1,
ramping+ve i/p ofOA4.OA4buffersVSLOPE and
setstheGATEoutputramp.
Flip-flop setting and resetting
Theflip-flop,SRFF1(fig2),usedintheIXHQ100,
is reset dominant. Hence when both S and R
inputs are driven high, the SRFF1 remains
reset. Undernormaloperation,Sinputbecomes
high whenever OR1 output is high and R input
is low. In turn, OR1 goes high if any one of the
outputs of EXOR1, or COMP2, or COMP3
goes high.
It is assumed that when the circuit board is first
inserted into the backplane, the voltage across
EXOR1 output goes high if it detects the loss of
either Gnd or -Vin. If INV input is connected to
*Unless otherwise stated, all symbol and device references are referred to the logic diagram (Fig 2) on page 6
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