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DX-DI-PCI32-SL

型号：

DX-DI-PCI32-SL

描述：

周边其他\n[ Peripheral Miscellaneous ]

品牌：

ETC[ ETC ]

页数：

5 页

PDF大小：

147 K

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0
LogiCORE PCI32 Interface v3.0  
0
0
DS 206 (v1.2) July 19, 2002  
Data Sheet, v3.0.100  
Introduction  
LogiCORE Facts  
1
With the Xilinx LogiCORE PCI Interface, a designer can  
build a customized, fully PCI 2.3-compliant core with the  
highest possible sustained performance, 528 Mbytes/sec.  
PCI64 Resource Utilization  
Slice Four Input LUTs  
Slice Flip Flops  
IOB Flip Flops  
IOBs  
724  
732  
176  
89  
Features  
•
Fully PCI 2.3-compliant core, 64/32-bit, 66/33 MHz  
interface  
TBUFs  
352  
•
•
•
•
•
•
Customizable, programmable, single-chip solution  
Predefined implementation for predictable timing  
Incorporates Xilinx Smart-IP Technology  
3.3 V operation at 0-66 MHz  
2
GCLKs  
1
1
PCI32 Resource Utilization  
Slice Four Input LUTs  
Slice Flip Flops  
IOB Flip Flops  
IOBs  
553  
566  
97  
5.0 V operation at 0-33 MHz  
Fully verified design tested with Xilinx proprietary  
testbench and hardware  
50  
TBUFs  
288  
•
Available for configuration and download on the web:  
2
-
-
Web-based Configuration and Download Tool  
Web-based User Constraint File Generator Tool  
GCLKs  
1
Provided with Core  
•
•
CardBus compliant  
Documentation  
PCI Design Guide  
Supported initiator functions:  
PCI Implementation Guide  
-
-
-
-
Configuration Read, Configuration Write  
Memory Read, Memory Write, MRM, MRL  
Interrupt Acknowledge, Special Cycles  
I/O Read, I/O Write  
Design File Formats  
Constraint Files  
Verilog/VHDL Simulation Model  
NGO Netlist  
User Constraint Files (UCF)  
Guide Files (NCD)  
•
Supported target functions:  
Example Design  
Verilog/VHDL Example Design  
-
-
Type 0 Configuration Space Header  
Design Tool Requirements  
Up to 3 Base Address Registers (MEM or I/O with  
adjustable block size from 16 bytes to 2 Gbytes)  
Xilinx Tools  
v4.2i, Service Pack 3  
Tested Entry and  
Verification Tools  
Synplicity Synplify  
Synopsys FPGA Express  
-
-
-
-
-
-
-
Medium Decode Speed  
3
Parity Generation, Parity Error Detection  
Configuration Read, Configuration Write  
Memory Read, Memory Write, MRM, MRL  
Interrupt Acknowledge  
Exemplar Leonardo Spectrum  
4
Xilinx XST  
Cadence Verilog XL  
Model Technology ModelSim  
1. The resource utilization depends on configuration of the interface and the user  
design. Unused resources are trimmed by the Xilinx technology mapper. The utili-  
zation figures reported in this table are representative of a maximum configuration.  
2. Designs running at 66 MHz in devices other than Virtex-II require one GCLKIOB  
and two GCLKs.  
I/O Read, I/O Write  
Target Abort, Target Retry, Target Disconnect  
3. See the implementation guide or product release notes for current supported ver-  
sions.  
4. XST is command line option only. See Implementation Guide for details.  
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other  
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this fea-  
ture, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may  
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warran-  
ties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.  
DS 206 (v1.2) July 19, 2002  
www.xilinx.com  
1
Data Sheet, v3.0.100  
1-800-255-7778  
LogiCORE PCI32 Interface v3.0  
LogiCORE Facts (Cont)  
ultra-fast RAM with synchronous write and dual-port  
RAM capabilities. Used in PCI designs to implement  
FIFOs.  
Supported Devices  
PCI32/66  
PCI32/33  
Virtex V200FG256-6C  
Virtex-E V200EFG256-6C  
Virtex-E V400EFG676-6C  
3.3v only  
3.3v only  
3.3v only  
•
•
SelectRAM memory. Distributed on-chip ultra-fast RAM  
with synchronous write option and dual-port RAM  
capabilities. Used in PCI designs to implement FIFOs.  
Virtex V300BG432-5C  
Virtex V1000FG680-5C  
3.3v, 5.0v  
3.3v, 5.0v  
3.3v only  
3.3v only  
3.3v only  
3.3v only  
3.3v only  
3.3v, 5.0v  
3.3v, 5.0v  
3.3v, 5.0v  
3.3v, 5.0v  
3.3v, 5.0v  
3.3v only  
3.3v only  
3.3v only  
3.3v only  
3.3v only  
Internal three-state bus capability for data multiplexing.  
Virtex-E V100EBG352-6C  
Virtex-E V300EBG432-6C  
Virtex-E V1000EFG680-6C  
Virtex-II 2V1000FG456-4C/I/M  
Virtex-II Pro 2VP7FF672-6C  
Spartan-II 2S30PQ208-5C  
Spartan-II 2S50PQ208-5C  
Spartan-II 2S100PQ208-5C  
Spartan-II 2S150PQ208-5C  
Spartan-II 2S200PQ208-5C  
Spartan-IIE 2S50EPQ208-6C  
Spartan-IIE 2S100EPQ208-6C  
Spartan-IIE 2S150EPQ208-6C  
Spartan-IIE 2S200EPQ208-6C  
Spartan-IIE 2S300EPQ208-6C  
The interface is carefully optimized for best possible perfor-  
mance and utilization in Xilinx FPGA devices.  
Smart-IP Technology  
Drawing on the architectural advantages of Xilinx FPGAs,  
Xilinx Smart-IP technology ensures the highest perfor-  
mance, predictability, repeatability, and flexibility in PCI  
designs. The Smart-IP technology is incorporated in every  
LogiCORE PCI interface.  
Xilinx Smart-IP technology leverages the Xilinx architectural  
advantages, such as look-up tables and segmented routing,  
as well as floorplanning information, such as logic mapping  
and location constraints. This technology provides the best  
physical layout, predictability, and performance. In addition,  
these features allow for significantly reduced compile times  
over competing architectures.  
Xilinx provides technical support for this LogiCORE product when used as described  
in the Design Guide and the Implementation Guide. Xilinx cannot guarantee timing,  
functionality, or support of product if implemented in devices not listed, or if custom-  
ized beyond that allowed in the product documentation.  
Note: Universal card implementations require two bitstreams.  
Note: Virtex-E and Spartan-IIE recommended for CardBus.  
Note: Commercial devices; 0 C < Tj < 85 C.  
Note: For additional Part/Package combinations, see the UCF Generator in the PCI  
Lounge.  
To guarantee the critical setup, hold, minimum clock-to-out,  
and maximum clock-to-out timing, the PCI interface is deliv-  
ered with Smart-IP constraint files that are unique for a  
device and package combination. These constraint files  
guide the implementation tools so that the critical paths  
always are within specification.  
Note: 2V1000 is supported over Military Temp. range.  
Applications  
•
Embedded applications in networking, industrial,  
and telecommunication systems  
•
PCI add-in boards such as frame buffers, network  
adapters, and data acquisition boards  
Xilinx provides Smart-IP constraint files for many device  
and package combinations. Constraint files for unsupported  
device and package combinations may be generated using  
the web-based constraint file generator.  
•
•
•
Hot swap CompactPCI boards  
CardBus compliant  
Any applications that need a PCI interface  
Functional Description  
General Description  
The LogiCORE PCI Interface is partitioned into five major  
blocks and a user application as shown in Figure 1.  
The LogiCORE PCI Interface is a preimplemented and fully  
tested module for Xilinx FPGAs. The pinout for each device  
and the relative placement of the internal logic are pre-  
defined. Critical paths are controlled by constraint and guide  
files to ensure predictable timing. This significantly reduces  
the engineering time required to implement the PCI portion  
of your design. Resources can instead be focused on your  
unique user application logic in the FPGA and on the sys-  
tem-level design. As a result, LogiCORE PCI products min-  
imize your product development time.  
PAR  
PAR64  
Base  
Address  
Register  
0
Base  
Address  
Register  
1
Base  
Address  
Register  
2
Parity  
Generator/  
Checker  
Command/  
Status  
Register  
PERR-  
SERR-  
AD[63:0]  
ADIO[63:0]  
FRAME-  
Interrupt  
Pin and  
Line  
Vendor ID,  
Rev ID,  
Other User  
Data  
Latency  
Timer  
Register  
IRDY-  
REQ-  
Initiator  
State  
Machine  
Register  
GNT-  
REQ64-  
PCI Configuration Space  
ACK64-  
TRDY-  
Target  
State  
Machine  
The core meets the setup, hold, and clock-to-timing require-  
ments as specified in the PCI-X specification. The interface  
is verified through extensive simulation.  
DEVSEL-  
STOP-  
Figure 1: LogiCORE PCI Interface Block Diagram  
Other features that enable efficient implementation of a PCI  
system include:  
•
Block SelectRAM™ memory. Blocks of on-chip  
2
www.xilinx.com  
1-800-255-7778  
DS 206 (v1.2) July 19, 2002  
Data Sheet, v3.0.100  
LogiCORE PCI32 Interface v3.0  
PCI I/O Interface Block  
1Ch  
Base Address Register 3 (BAR3)  
20h  
The I/O interface block handles the physical connection to  
the PCI bus including all signaling, input and output syn-  
chronization, output three-state controls, and all  
request-grant handshaking for bus mastering.  
Base Address Register 4 (BAR5)  
Base Address Register 5 (BAR5)  
Cardbus CIS Pointer  
24h  
28h  
2Ch  
30h  
Subsystem ID  
Subsystem Vendor ID  
User Application  
Expansion ROM Base Address  
Reserved  
The LogiCORE PCI Interface provides a simple, gen-  
eral-purpose interface for a wide range of applications.  
34h  
CapPtr  
Int Line  
38h  
Reserved  
PCI Configuration Space  
3Ch  
40h-FFh  
Max Lat  
Min Gnt  
Int Pin  
This block provides the first 64 bytes of Type 0, version 2.3  
Configuration Space Header, as shown in Ta ble 1, to sup-  
port software-driven “Plug-and-Play” initialization and con-  
figuration. This includes information for Command, Status,  
and three Base Address Registers (BARs).  
Reserved  
Note:  
Shaded areas are not implemented and return zero.  
Interface Configuration  
The LogiCORE PCI Interface can easily be configured to fit  
unique system requirements by using the Xilinx Web-based  
Configuration and Download tool or by changing the HDL  
configuration file. The following customization options,  
among many others, are supported by the interface and are  
described in the product design guide.  
The capability for extending configuration space has been  
built into the user application interface. This capability,  
including the ability to implement a capabilities pointer in  
configuration space, allows the user to implement functions  
such as power management and message signaled inter-  
rupts in the user application.  
•
•
Base Address Registers (number, size, and type)  
Configuration Space Header ROM  
Parity Generator/Checker  
This block generates and checks even parity across the AD  
bus, the CBE# lines, and the parity signals. It also reports  
data parity errors via PERR# and address parity errors via  
SERR#.  
Burst Transfer  
The PCI bus derives its performance from its ability to sup-  
port burst transfers. The performance of any PCI applica-  
tion depends largely on the size of the burst transfer. Buffers  
to support PCI burst transfer can efficiently be implemented  
using on-chip RAM resources.  
Initiator State Machine  
This block controls the PCI interface initiator functions. The  
states implemented are a subset of those defined in Appen-  
dix B of the PCI Local Bus Specification. The initiator control  
logic uses one-hot encoding for maximum performance.  
Supported PCI Commands  
Table 2 illustrates the PCI bus commands supported by the  
LogiCORE PCI Interface.  
Target State Machine  
This block controls the PCI interface target functions. The  
states implemented are a subset of those defined in Appen-  
dix B of the PCI Local Bus Specification. The target control  
logic uses one-hot encoding for maximum performance.  
Bandwidth  
The LogiCORE PCI Interface supports fully compliant zero  
wait-state burst operations for both sourcing and receiving  
data. This interface supports a sustained bandwidth of up to  
528 MBytes/sec. The design can be configured to take  
advantage of the ability of the LogiCORE PCI Interface to  
do very long bursts.  
Table 1: PCI Configuration Space Header  
31  
16 15  
0
00h  
04h  
08h  
0Ch  
Device ID  
Status  
Vendor ID  
Command  
The flexible user application interface, combined with sup-  
port for many different PCI features, gives users a solution  
that lends itself to use in many high-performance applica-  
tions. The user is not locked into one DMA engine; hence,  
an optimized design that fits a specific application can be  
designed.  
Class Code  
Rev ID  
BIST  
Header Type Latency Tim- Cache Line  
er  
Size  
10h  
14h  
18h  
Base Address Register 0 (BAR0)  
Base Address Register 1 (BAR1)  
Base Address Register 2 (BAR2)  
DS 206 (v1.2) July 19, 2002  
Data Sheet, v3.0.100  
www.xilinx.com  
1-800-255-7778  
3
LogiCORE PCI32 Interface v3.0  
Table 3: Timing Parameters, 66MHz Implementations  
Recommended Design Experience  
Symbol  
Tcyc  
Parameter  
CLK Cycle Time  
Min  
151  
6
Max  
30  
-
The LogiCORE PCI Interface is preimplemented, allowing  
engineering focus on the unique user application functions  
of a PCI design. Regardless, PCI is a high-performance  
design that is challenging to implement in any technology.  
Therefore, previous experience with building high-perfor-  
mance, pipelined FPGA designs using Xilinx implementa-  
tion software, constraint files, and guide files is  
recommended. The challenge to implement a complete PCI  
design including user application functions varies depend-  
ing on configuration and functionality of your application.  
Contact your local Xilinx representative for a closer review  
and estimation for your specific requirements.  
Thigh  
Tlow  
CLK High Time  
CLK Low Time  
6
-
Tval  
CLK to Signal Valid Delay  
(bussed signals)  
22  
62  
Tval  
CLK to Signal Valid Delay  
(point to point signals)  
22  
62  
Float to Active Delay  
Active to Float Delay  
22  
-
32,3  
-
141  
-
Ton  
Toff  
Tsu  
Input Setup Time to CLK  
(bussed signals)  
Tsu  
Input Setup Time to CLK  
(point to point signals)  
52,3  
-
02,3  
-
-
Th  
Input Hold Time from CLK  
Reset Active to Output Float  
Timing Specifications  
Trstoff  
40  
The maximum speed at which your user design is capable  
of running can be affected by the size and quality of the  
design. The following tables show the key timing parame-  
ters for the LogiCORE PCI Interface.  
Notes:  
1. Controlled by timespec constraints, included in product.  
2. Controlled by SelectIO configured for PCI66_3.  
3. Controlled by guide file, included in product.  
Table 4: Timing Parameters, 33MHz Implementations  
Table 3 lists the Timing Parameters in the 66MHz Imple-  
mentations and Table 4 lists Timing Parameters in the  
33MHz Implementations.  
Symbol  
Tcyc  
Parameter  
CLK Cycle Time  
Min  
301  
11  
Max  
-
-
Thigh  
Tlow  
CLK High Time  
CLK Low Time  
11  
-
Tval  
CLK to Signal Valid Delay  
(bussed signals)  
22  
112  
Table 2: PCI Bus Commands  
PCI  
Initiator  
PCI  
Target  
Tval  
CLK to Signal Valid Delay  
(point to point signals)  
22  
112  
CBE [3:0]  
Command  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
Interrupt Acknowledge  
Special Cycle  
Yes  
Yes  
Yes  
Ignore  
Yes  
Ton  
Toff  
Tsu  
Float to Active Delay  
Active to Float Delay  
22  
-
72  
-
281  
-
I/O Read  
Yes  
Input Setup Time to CLK  
(bussed signals)  
I/O Write  
Yes  
Yes  
Reserved  
Ignore  
Ignore  
Yes  
Ignore  
Ignore  
Yes  
Tsu  
Input Setup Time to CLK  
(point to point signals)  
102  
-
Reserved  
02  
-
-
Memory Read  
Memory Write  
Reserved  
Th  
Input Hold Time from CLK  
Reset Active to Output Float  
Yes  
Yes  
Trstoff  
40  
Ignore  
Ignore  
Yes  
Ignore  
Ignore  
Yes  
Notes:  
1. Controlled by timespec constraints, included in product.  
2. Controlled by SelectIO configured for PCI33_3 or PCI33_5.  
Reserved  
Configuration Read  
Configuration Write  
Memory Read Multiple  
Dual Address Cycle  
Memory Read Line  
Memory Write Invalidate  
Yes  
Yes  
Yes  
Yes  
No  
Ignore  
Yes  
Yes  
No  
Yes  
4
www.xilinx.com  
1-800-255-7778  
DS 206 (v1.2) July 19, 2002  
Data Sheet, v3.0.100  
LogiCORE PCI32 Interface v3.0  
DX-DI-PCI32-SL  
Ordering Information  
-Upgrade from PCI32 33 MHz Spartan only to V3.0  
PCI32 33 MHz Spartan and 66 MHz Virtex Families  
This core may be downloaded from the Xilinx IP Center for  
use with the Xilinx CORE Generator System v4.1 and later.  
The Xilinx CORE Generator System tool is bundled with all  
Alliance and Foundation Series Software packages, at no  
additional charge.  
DO-DI-PCI32-SP  
-Access to the V3.0 PCI32 Spartan Family  
Part Numbers  
To order the Xilinx PCI Core, please visit the Xilinx Silicon  
Xpresso Cafe or contact your local Xilinx sales representa-  
tive.  
DO-DI-PCI32-IP  
-Access to the V3.0 PCI32 33 MHz Spartan and 66 MHz  
Virtex Families  
Revision History  
The following table shows the revision history for this document.  
Date  
Version  
Revision  
06/27/02  
1.0  
New template  
DS 206 (v1.2) July 19, 2002  
Data Sheet, v3.0.100  
www.xilinx.com  
1-800-255-7778  
5
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