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CYM9273

型号：

CYM9273

描述：

内存\n[ Memory ]

品牌：

ETC[ ETC ]

页数：

11 页

PDF大小：

172 K

下载PDF手册
72A  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
64K x 36 SRAM Module  
128K x 36 SRAM Module  
256K x 36 SRAM Module  
512K x 36 SRAM Module  
(9273) in plastic surface mount packages on an epoxy lami-  
nate board with pins. The modules are designed to be incor-  
porated into large memory arrays.  
Features  
• Operates at 50 MHz  
• Uses64Kx18/128Kx18or256Kx18high-performance  
The modules are configured as single banks or multiple banks  
depending on the SRAM used to make the module. Separate  
clock are provided for each of the banks. Separate clocks are  
provided for each of the SRAMs.  
synchronous SRAMs  
• 144-Position Angled DIMM from Berg p/n 61178  
• 3.3V inputs/data outputs  
Multiple ground pins and on-board decoupling capacitors en-  
sure high performance with maximum noise immunity.  
Functional Description  
The CYM9270, CYM9271B, CYM9272A, and the CYM9273  
are high-performance synchronous memory modules orga-  
nized as 64K(9270), 128K(9271B), 256K(9272A), 512K(9273)  
by 36 bits. These modules are constructed using either 128K  
x 18 SRAMs (9270, 9271B, 9272A) or 256K x 18 SRAMs  
All components on the cache modules are surface mounted on  
a multi-layer epoxy laminate (FR-4) substrate. The contact  
pins are plated with 150 micro-inches of nickel covered by 30  
micro-inches of gold flash.  
Logic Block Diagram -CYM9270  
A[15:0]  
(2) 128K x 18 SRAMs  
A
15:0  
WE  
SGW  
D[0:31]  
DQ[0:3]  
OE  
CS  
OE  
D[0:15]  
DQ[0:1]  
OE  
CS  
CS  
BW[0:3]  
BWE  
WEH  
WEL  
ADSC  
ADSP  
CLK[0:1]  
CLK  
Bank 0  
CLK[0:1]  
PD  
1
PD  
0
GND NC  
Bank0  
64Kx36  
Cypress Semiconductor Corporation  
Document #: 38-05135 Rev. **  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised March 27, 2002  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
LogicBlockDiagram- CYM9271B/CYM9272A  
A[16:0]  
(2) 128K x 18 SRAMs  
A
16:0  
WE  
SGW  
D[0:31]  
DQ[0:3]  
OE0  
CS0  
OE[0:1]  
CS[0:1]  
BW[0:3]  
D[0:15]  
DQ[0:1]  
OE  
CS  
BWE  
WEH  
WEL  
ADSC  
ADSP  
CLK[0:3]  
CLK  
Bank0  
CLK[0:1]  
(2) 128K x 18 SRAMs  
A
16:0  
SGW  
OE  
OE1  
CS1  
D[0:15]  
DQ[0:1]  
CS  
BWE  
WEH  
WEL  
ADSC  
CLK  
Bank1  
CLK[2:3]  
PD  
PD  
1
0
Bank0  
NC  
GND  
128Kx36  
256KX36  
GND GND Bank0 and Bank1  
Document #: 38-05135 Rev. **  
Page 2 of 11  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
LogicBlockDiagram- CYM9273  
A[17:0]  
(2) 256K x 18 SRAMs  
A
17:0  
WE  
SGW  
D[0:31]  
DQ[0:3]  
OE0  
OE[0:1]  
CS[0:1]  
BW[0:3]  
D[0:15]  
DQ[0:1]  
OE  
CS  
CS[0]  
BWE  
WEH  
WEL  
ADSC  
ADSP  
CLK[0:3]  
CLK  
Bank0  
CLK[0:1]  
(2) 256K x 18 SRAMs  
A
17:0  
SGW  
OE1  
D[0:15]  
DQ[0:1]  
OE  
CS  
CS[1]  
BWE  
WEH  
WEL  
ADSC  
CLK  
Bank1  
CLK[2:3]  
PD  
PD  
NC  
0
1
512KX36  
Bank0 and 1  
NC  
Document #: 38-05135 Rev. **  
Page 3 of 11  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
Pin Configuration  
Dual Read-Out SIMM (DIMM)  
Top View  
1
3
2
GND  
GND  
A
0
4
A
1
A
A
5
6
8
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
2
3
A
4
CC3  
NC  
A
5
7
V
9
V
CC3  
11  
13  
NC  
NC  
NC  
GND  
GND  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
A
6
A
7
A
8
A
9
A
A
11  
10  
NC  
CC3  
NC  
V
V
A
13  
CC3  
A
12  
A
14  
A
15  
A
A
16  
17  
GND  
PD  
0
GND  
BW[0]  
CS[0]  
GND  
CLK1  
GND  
GND  
PD  
1
38  
40  
GND  
BW[1]  
OE[0]  
42  
44  
46  
48  
50  
52  
54  
56  
GND  
CLK0  
GND  
45  
47  
49  
51  
53  
55  
57  
59  
D
CC3  
D
CC3  
0
1
V
V
D
D
2
3
5
D
D
D
D
4
6
58  
60  
7
GND  
GND  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
90  
92  
94  
96  
98  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
61  
63  
65  
67  
69  
71  
V
V
CC3  
9
CC3  
D
D
8
D
D
10  
11  
GND  
GND  
D
D
12  
13  
15  
D
D
14  
DQ  
73  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
97  
99  
101  
103  
105  
107  
109  
DQ  
NC  
NC  
GND  
ADSP  
NC  
V
0
1
NC  
NC  
GND  
WE  
NC  
V
CC3  
CC3  
NC  
NC  
NC  
NC  
NC  
NC  
V
V
CC3  
NC  
NC  
CC3  
NC  
NC  
NC  
NC  
GND  
BW[3]  
OE[1]  
GND  
BW[2]  
CS[1]  
V
CC3  
V
CC3  
D
D
NC  
NC  
NC  
GND  
CLK2  
GND  
D
GND  
D
D
D
D
V
D
D
NC  
NC  
NC  
GND  
CLK3  
GND  
D
GND  
D
D
D
D
16  
18  
17  
19  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
20  
21  
22  
24  
23  
25  
27  
29  
132  
134  
26  
28  
136  
138  
140  
142  
144  
CC3  
V
CC3  
D
D
30  
31  
DQ  
GND  
DQ  
2
3
GND  
Document #: 38-05135 Rev. **  
Page 4 of 11  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
Pin Definitions  
Signal  
Description  
VCC3  
3V Supply  
GND  
Ground  
A[17:0]  
ADSP  
OE[1:0]  
BW[0:3]  
WE  
Addresses from processor  
Address strobe from the processor  
Output Enables for each of the banks  
Byte writes  
Global Write  
CS[1:0]  
PD0–PD1  
D[31:0]  
DQ[3:0]  
CLK[0:3]  
NC  
Chip Select for the two banks  
Presence Detect output pins  
Data lines from processor  
Data Parity lines from processor  
Clock lines to the module.  
Signal not connected on module  
Reserved  
RSVD  
Presence Detect Pins  
PD1  
GND  
NC  
PD0  
NC  
CYM9270 – 64K x 36  
CYM9271B – 128K x 36  
CYM9272A – 256K x 36  
CYM9273 – 512K x 36  
GND  
GND  
NC  
GND  
NC  
Document #: 38-05135 Rev. **  
Page 5 of 11  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
DC Input Voltage ........................................... –0.5V to +4.6V  
Maximum Ratings  
Output Current into Outputs (LOW)............................. 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Operating Range  
Storage Temperature................................. –55°C to +125°C  
Range  
Ambient Temperature  
VCC  
Ambient Temperature  
with Power Applied ........................................ –0°C to +70°C  
Commercial  
0°C to +70°C  
3.3V ± ±5%  
3.3V Supply Voltage to Ground Potential ..... –0.5V to +4.5V  
DC Voltage Applied to Outputs  
in High Z State.............................................. –0.5V to +4.6V  
Electrical Characteristics Over the Operating Range  
Parameter  
VIH  
Description  
Input HIGH Voltage  
Input LOW Voltage  
Output HIGH Voltage  
Output LOW Voltage  
Test Condition  
Min.  
2.2  
Max.  
Unit  
V
VCC + 0.3  
0.8  
VIL  
–0.3  
2.4  
V
VOH  
VCC = Min., IOH = −4 mA  
VCC = Min., IOL = 8 mA  
V
VOL  
0.4  
350  
V
ICC (9270)  
ICC (9271B)  
ICC (9272A)  
ICC (9273)  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC  
mA  
mA  
mA  
mA  
500  
1000  
1200  
Capacitance[1]  
Parameter  
Description  
Test Conditions  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
Max.  
12  
7
Unit  
CA  
Address Input Capacitance  
Control Input Capacitance  
Input / Output Capacitance  
Clock Capacitance  
9270  
9271B  
9272A  
9273  
pF  
14  
20  
12  
8
CI  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
9270  
9271B  
9272A  
9273  
16  
20  
9
CO  
TA = 25°C, f = 1 MHz,  
VCC = 5.0V  
9270  
9271B  
9272A  
9273  
5
10  
16  
6
CCLK  
TA = 25°C, f = 1 MHz,  
9270  
VCC = 5.0V  
9271B  
9272A  
9273  
3
3
5
Note:  
1. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05135 Rev. **  
Page 6 of 11  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
AC Test Loads and Waveforms[3]  
R1  
V
CCQ  
OUTPUT  
ALL INPUT PULSES  
OUTPUT  
3.3V  
GND  
90%  
10%  
R = 50±Ω  
L
90%  
10%  
R2  
5 pF  
V = 1.5V  
L
INCLUDING  
JIGAND  
≤ 3 ns  
≤ 3 ns  
(a)  
(b)[2]  
SCOPE  
Switching Characteristics Over the Operating Range  
CYM9270  
Min. Max.  
CYM9271B  
CYM9272A  
CYM9273  
Parameter  
tCYC  
Description  
Clock Cycle Time  
Min.  
12  
4
Max.  
Min.  
12  
4
Max.  
Min.  
12  
4
Max. Unit  
12  
4
ns  
ns  
ns  
ns  
ns  
tCH  
Clock HIGH  
tCL  
Clock LOW  
4
4
4
4
tAS  
Address Set-Up Before CLK Rise  
Address Hold After CLK Rise  
Data Output Valid After CLK Rise  
Data Output Hold After CLK Rise  
WH, WL Set-Up Before CLK Rise  
WH, WL Hold After CLK Rise  
Data Input Set-Up Before CLK Rise  
Data Input Hold After CLK Rise  
Chip Select Set-Up  
3
3
3
3
tAH  
0.5  
0.5  
0.5  
0.5  
tCDV  
tDOH  
tWES  
tWEH  
tDS  
10.3  
10.3  
10.3  
10.3  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3
3
3
3
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
3.1  
0.5  
3.3  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
3.1  
0.5  
3.3  
0.5  
3.1  
0.5  
tDH  
tCSS  
tCSH  
3.1  
0.5  
Chip Select Hold After CLK Rise  
OE HIGH to Output High Z  
OE LOW to Output Valid  
[4]  
tEOZ  
7
7
7
7
tEOV  
7
7
7
7
Notes:  
2. Resistor values for VCCQ = 3.3V are R1 = 317Ω and R2 = 351Ω.  
3. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output  
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. All measurements are at room temperature.  
4.  
tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.  
Document #: 38-05135 Rev. **  
Page 7 of 11  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
Switching Waveforms  
Single Read[5]  
t
t
CL  
t
CYC  
CH  
CLK  
t
t
CSH  
CSS  
CS  
ADDRESS  
ADSP  
t
t
AH  
AS  
t
t
ADSH  
ADS  
t
t
WEH  
WES  
[6]  
WH, WL  
t
t
DOH  
CDV  
DATA OUT  
Single Write Timing  
t
t
CL  
CH  
CLK  
CS  
t
t
CSH  
CSS  
t
AS  
t
AH  
ADDRESS  
t
t
ADSH  
ADS  
ADSP  
t
t
WEH  
WES  
WH, WL  
t
t
DH  
DS  
DATA IN  
DATA OUT  
t
EOZ  
OE  
Notes:  
5. OE is LOW throughout this operation.  
6. ADSP has no effect on ADV, WL, and WH if CS is HIGH.  
Document #: 38-05135 Rev. **  
Page 8 of 11  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
Switching Waveforms (continued)  
Output (Controlled by OE)  
DATA OUT  
OE  
t
t
EOV  
EOZ  
Output Timing (Controlled by CS)  
CLK  
t
t
ADSH  
ADS  
t
t
ADS  
ADSH  
ADSP  
CS  
t
t
CSH  
CSS  
t
t
CSH  
CSS  
t
t
CSOZ  
CDV  
DATA OUT  
Output Timing (Controlled by WH/ WL)  
CLK  
t
ADSH  
t
t
t
ADSH  
ADS  
ADS  
ADSP  
t
t
WES  
WEH  
WH, WL  
t
t
WEOZ  
WEOV  
DATA OUT  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(MHz)  
Ordering Code  
CYM9270PM-50C  
CYM9271BPM-50C  
CYM9272APM-50C  
CYM9273PM-50C  
Package Type  
Description  
Sync 64K x 36  
50  
PM45  
PM45  
PM46  
PM46  
144-Pin Dual-Readout SIMM  
144-Pin Dual-Readout SIMM  
144-Pin Dual-Readout SIMM  
144-Pin Dual-Readout SIMM  
Commercial  
Sync 128K x 36  
Sync 256K x 36  
Sync 512K x 36  
Document #: 38-05135 Rev. **  
Page 9 of 11  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
Package Diagrams  
144-Pin Single-Sided DIMM PM45  
144-Pin Dual-Sided DIMM PM46  
Document #: 38-05135 Rev. **  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
CYM9270  
CYM9271B  
CYM9272A  
CYM9273  
Document Title: CYM9270, CYM9271B, CYM9272A, CYM9273 64K/128K/256K/512K x 36 SRAM Module  
Document Number: 38-05135  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
114557  
3/28/02  
DSG  
Change from Spec number: 38-M-00083 to 38-05135  
Document #: 38-05135 Rev. **  
Page 11 of 11  
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