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CYK001M16ZCCAU

型号：

CYK001M16ZCCAU

描述：

内存\n[ Memory ]

品牌：

ETC[ ETC ]

页数：

10 页

PDF大小：

173 K

下载PDF手册
CYK001M16ZCCAU  
MoBL3™  
ADVANCE  
INFORMATION  
16-Mb (1Mb x 16) Pseudo Static RAM  
Battery Life(MoBL) in portable applications such as cellular  
telephones. The device can be put into standby mode  
reducing power consumption by more than 99% when  
deselected CE HIGH or both BHE and BLE are HIGH. The  
input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when: deselected (CE HIGH), outputs  
are disabled (OE HIGH), or during a write operation (Chip  
Enables (CE LOW) and Write Enable (WE) LOW). The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling even when the chip is selected (Chip Enable CE LOW  
and both BHE and BLE are LOW). Reading from the device is  
accomplished by taking Chip Enables (CE LOW) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.  
If Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins will appear on I/O0 to  
I/O7. If Byte High Enable (BHE) is LOW, then data from  
Features  
• Advanced low-power MoBL® architecture  
• High speed: 70 ns  
• Wide Voltage range:  
— VCC range: 2.7V to 3.3V  
— VCC (I/O) range: 2.7V to VCC  
• Low active power  
— Typical active current: 2 mA @ f = 1 MHz  
— Typical active current: 13 mA @ f = fMAX  
• Low standby power  
• Automatic power-down when deselected  
• Deep Sleep Mode Operation  
memory will appear on I/O8 to I/O15  
.
Functional Description[1]  
This device incorporates a Low Power mode wherein data  
integrity is not guaranteed, but Power Consumption reduces  
to less than 100 µW. This mode (Deep Sleep Mode) is enabled  
by driving ZZ low.See the Truth Table for a complete  
description of Read, Write, and Deep Sleep modes.  
The CYK001M16ZCCAU MoBL3 is a high-performance  
CMOS pseudo static RAMs (PSRAM) organized as 1M words  
by 16 bits that supports an asynchronous memory interface.  
This device features advanced circuit design to provide  
ultra-low active current. This is ideal for providing More  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
A
9
8
7
6
5
4
A
A
A
A
A
1M x 16  
RAM Array  
I/O –I/O  
0
7
A
A
A
3
2
1
0
I/O –I/O  
8
15  
A
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
ZZ  
CE  
Power -Down  
Circuit  
BHE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05454 Rev. **  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 8, 2004  
ADVANCE  
INFORMATION  
CYK001M16ZCCAU  
MoBL3™  
Pin Configuration[2, 3, 4]  
FBGA  
Top View  
1
2
4
3
5
6
A
A
A
2
ZZ  
I/O  
OE  
BLE  
0
1
A
B
C
A
A
I/O BHE  
8
CE  
I/O  
4
3
0
A
A
6
I/O I/O  
I/O  
2
5
10  
1
9
V
A
V
I/O  
I/O  
3
A
CC  
D
E
F
SS  
7
11  
17  
V
DNU  
A
16  
V
CC  
SS  
I/O  
I/O  
12  
4
A
A
15  
I/O  
I/O  
5
I/O  
I/O  
6
14  
13  
14  
A
A
G
H
I/O  
A
WE I/O  
7
13  
12  
15  
19  
A
A
9
A
11  
A
A
NC  
10  
8
18  
Notes:  
2. DNU pins are to be left floating or tied to VSS  
.
3. Ball H6 is the address expansion pin for the 32M density.  
4. NC “no connect” – not connected internally to the die.  
Document #: 38-05454 Rev. **  
Page 2 of 10  
ADVANCE  
INFORMATION  
CYK001M16ZCCAU  
MoBL3™  
DC Input Voltage[5, 6, 7] ....................................−0.4V to 3.6V  
Maximum Ratings  
Output Current into Outputs (LOW) ............................ 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage ......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................–65°C to +150°C  
Latch-up Current ....................................................> 200 mA  
Ambient Temperature with  
Power Applied ..............................................–40°C to +85°C  
Operating Range[9]  
Supply Voltage to Ground Potential ................ −0.4V to 4.6V  
DC Voltage Applied to Outputs  
in High-Z State[5, 6, 7] ....................................... −0.4V to 3.0V  
Range  
Ambient Temperature (TA)  
VCC  
Industrial  
−25°C to +85°C  
2.7V to 3.3V  
Product Portfolio  
Power Dissipation  
Operating, Icc (mA)  
VCC Range  
(V)  
f = 1 MHz  
f = fMAX  
Standby, ISB2 (µA)  
Speed  
(ns)  
Product  
Min.  
Typ.  
Max.  
Typ.[8]  
Max.  
Typ.[8]  
Max.  
Typ.[8]  
Max.  
CYK001M16ZCCAU  
2.7  
3.0  
3.3  
70  
2
3.5  
13  
17  
80  
150  
DC Electrical Characteristics (Over the Operating Range)  
CYK001M16ZCCAU  
Parameter  
Description  
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
Test Conditions  
Min.  
Typ.[8]  
Max.  
Unit  
V
VOH  
VOL  
VIH  
VIL  
IIX  
IOH = −1 mA  
VCC - 0.4  
IOL = 2 mA  
0.4  
VCC + 0.4  
0.4  
V
0.8*VCC  
−0.4  
−1  
V
F = 0  
V
Input Leakage Current  
Output Leakage Current  
GND < VI < VCC  
GND < VO < VCC, Output Disabled  
+1  
µA  
µA  
mA  
IOZ  
ICC  
−1  
+1  
VCC Operating Supply  
Current  
f = fMAX = 1/tRC Vcc = 3.3V, IOUT = 0 mA,  
CMOS level  
13  
17  
f = 1 MHz  
2
3.5  
ISB1  
Automatic CE Power-down CE > VCC − 0.2V,  
Current − CMOS Inputs  
100  
525  
µA  
VIN > VCC − 0.2V, VIN < 0.2V,  
f = fMAX(Address and Data Only),  
f = 0 (OE, WE, BHE and BLE)  
ISB2  
Automatic CE Power-down CE > VCC − 0.2V,  
80  
150  
30  
µA  
µA  
Current − CMOS Inputs  
VIN > VCC − 0.2V or VIN < 0.2V,  
f = 0, VCC =3.3V  
IZZ  
Deep Sleep Current  
VCC=VCCMAX , ZZ=LOW  
Capacitance [10]  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
CIN  
Input Capacitance  
Output Capacitance  
TA = 25°C, f = 1 MHz  
VCC = VCC(typ)  
8
8
pF  
pF  
COUT  
Notes:  
5. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns.  
6. VIL(MIN) = -0.5V for pulse durations less than 20 ns.  
7. Overshoot and undershoot specifications are characterized and are not 100% tested.  
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25C.  
9. Vcc must be at minimal operational levels before inputs are turned ON.  
10. Tested initially and after design or process changes that may affect these parameters.  
Document #: 38-05454 Rev. **  
Page 3 of 10  
ADVANCE  
INFORMATION  
CYK001M16ZCCAU  
MoBL3™  
Thermal Resistance[10]  
Parameter  
θJA  
Description  
Test Conditions  
FBGA  
Unit  
Thermal Resistance (Junction to  
Ambient)  
Still Air, soldered on a 3 x 4.5 inch, two-layer  
printed circuit board  
55  
°C/W  
θJC  
Thermal Resistance (Junction to  
Case)  
17  
°C/W  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
VCC  
90%  
90%  
VCC  
OUTPUT  
10%  
10%  
Fall Time = 1 V/ns  
GND  
Rise Time = 1 V/ns  
R2  
30 pF  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THÉVENIN EQUIVALENT  
RTH  
OUTPUT  
VTH  
Parameters  
3.0V VCC  
1179  
Unit  
W
R1  
R2  
1941  
733  
W
RTH  
VTH  
W
1.87  
V
Switching Characteristics (Over the Operating Range) [11]  
CYK001M16ZCCAU-70  
Parameter  
Read Cycle  
Description  
Min.  
Max.  
Unit  
tRC  
Read Cycle Time  
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
70  
tOHA  
Data Hold from Address Change  
CE LOW to Data Valid  
10  
tACE  
70  
35  
tDOE  
OE LOW to Data Valid  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tDBE  
OE LOW to Low Z[12, 14]  
OE HIGH to High Z[12, 14]  
CE LOW to Low Z[12, 14]  
CE HIGH to High Z[12, 14]  
BLE/BHE LOW to Data Valid  
BLE/BHE LOW to Low Z[12, 14]  
BLE/BHE HIGH to High-Z[12, 14]  
Address Skew  
5
5
25  
25  
70  
tLZBE  
tHZBE  
tSK  
5
25  
10  
Write Cycle[13]  
tWC  
Write Cycle Time  
70  
55  
ns  
ns  
tSCE  
CE LOW to Write End  
Note:  
11. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ)/2, input pulse levels of to VCC(typ), and output loading of the  
specified IOL/IOH and 30-pF load cpacitance.  
12. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state.  
13. The internal memory write time is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any of these  
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.  
14. High-Z and Low-Z parameters are characterized and are not 100% tested.  
Document #: 38-05454 Rev. **  
Page 4 of 10  
ADVANCE  
INFORMATION  
CYK001M16ZCCAU  
MoBL3™  
Switching Characteristics (Over the Operating Range) (continued)[11]  
CYK001M16ZCCAU-70  
Parameter  
Description  
Address Set-up to Write End  
Min.  
55  
0
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAW  
tHA  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
tSA  
0
tPWE  
tBW  
tSD  
55  
55  
25  
0
BLE/BHE LOW to Write End  
Data Set-up to Write End  
Data Hold from Write End  
WE LOW to High Z[12, 14]  
WE HIGH to Low Z[12, 14]  
tHD  
tHZWE  
tLZWE  
25  
5
Switching Waveforms  
[15]  
Read Cycle 1 (Address Transition Controlled)  
tRC  
ADDRESS  
t
AA  
tSK  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE Controlled)[15]  
ADDRESS  
t
RC  
CE  
tSK  
t
PD  
tACE  
tHZCE  
/
BHE BLE  
t
DBE  
t
HZBE  
t
LZBE  
OE  
t
HZOE  
t
DOE  
LZOE  
HIGH IMPEDANCE  
t
HIGH  
IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
ICC  
ISB  
t
PU  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
Note:  
15. WE is HIGH for Read Cycle.  
Document #: 38-05454 Rev. **  
Page 5 of 10  
ADVANCE  
INFORMATION  
CYK001M16ZCCAU  
MoBL3™  
Switching Waveforms (continued)  
Write Cycle No. 1 (WE Controlled)[13, 14, 16, 17, 18]  
t
WC  
ADDRESS  
t
SCE  
CE  
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
t
BW  
BHE/BLE  
OE  
t
SD  
t
HD  
VALID DATA  
DATAI/O  
DO N’T CARE  
t
HZOE  
Write Cycle No. 2 (CE Controlled)[13, 14, 16, 17, 18]  
t
WC  
ADDRESS  
t
SCE  
CE  
tSA  
t
t
HA  
AW  
tPWE  
WE  
t
BW  
BHE/BLE  
OE  
t
t
SD  
HD  
DATAI/O  
VALID DATA  
DON’T CARE  
t
HZOE  
Notes:  
16. Data I/O is high impedance if OE = VIH.  
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
18. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05454 Rev. **  
Page 6 of 10  
ADVANCE  
INFORMATION  
CYK001M16ZCCAU  
MoBL3™  
Switching Waveforms (continued)  
Write Cycle No. 3 (WE Controlled, OE LOW)[17, 18]  
t
WC  
ADDRESS  
t
SCE  
CE  
t
BW  
BHE/BLE  
t
t
HA  
AW  
t
t
PWE  
SA  
WE  
t
t
HD  
SD  
DATAI/O  
DON’T CARE  
VALID D ATA  
t
LZWE  
t
HZWE  
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[17, 18]  
t
WC  
ADDRESS  
CE1  
tSCE  
AW  
t
t
HA  
tBW  
BHE/BLE  
WE  
t
SA  
tPWE  
t
t
HD  
SD  
DON’T CARE  
DATA I/O  
VALID DATA  
Sleep Mode can be enabled by driving ZZ low. The device  
stays in the deep sleep mode until ZZ is driven High.  
Deep Sleep Mode  
This mode can be used to lower the power consumption of the  
PSRAM in an application. In this mode, the data integrity of the  
PSRAM is not guaranteed. At any point of time, the Deep  
Deep Sleep Mode—Entry/Exit[19]  
Document #: 38-05454 Rev. **  
Page 7 of 10  
ADVANCE  
INFORMATION  
CYK001M16ZCCAU  
MoBL3™  
Deep Sleep Mode  
ZZ  
t
R
t
CDR  
CE or  
BLE / BHE  
Deep Sleep Access Timings[20, 21]  
Parameter  
Description  
Min.  
Max.  
Unit  
ns  
tCDR  
tR  
Chip Deselect to ZZ LOW  
Operation Recovery Time  
0
200  
µs  
Truth Table[22]  
ZZ  
H
CE  
H
X
WE  
X
OE  
X
BHE BLE  
Inputs/Outputs  
High Z  
Mode  
Deselect/Power-down  
Deselect/Power-down  
Read  
Power  
Standby (ISB  
Standby (ISB  
Active (ICC  
Active (ICC  
X
H
L
X
H
L
)
H
X
X
High Z  
)
H
L
H
L
Data Out (I/O0–I/O15)  
)
H
L
H
L
H
L
Data Out (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Read  
)
H
L
H
L
L
H
Data Out (I/O8–I/O15);  
I/O0–I/O7 in High Z  
Read  
Active (ICC)  
H
H
H
H
L
L
L
L
H
H
H
L
H
H
H
X
L
H
L
L
L
High Z  
High Z  
High Z  
Output Disabled  
Output Disabled  
Output Disabled  
Active (ICC  
Active (ICC  
Active (ICC  
)
)
H
L
)
L
Data In (I/O0–I/O15  
)
Write (Upper Byte and Lower Active (ICC)  
Byte)  
H
H
L
L
L
L
X
X
X
X
H
L
L
H
H
Data In (I/O0–I/O7);  
I/O8–I/O15 in High Z  
Write (Lower Byte Only)  
Active (ICC  
Active (ICC  
Deep Sleep (IZZ)  
)
Data In (I/O8–I/O15);  
I/O0 –I/O7 in High Z  
Write (Upper Byte Only)  
Deep Power-down  
)
L
H
H
High Z  
Notes:  
19. OE and the data pins are in a “don’t care” state while the device is in Deep Sleep Mode.  
20. All other timing parameters are as shown in the switching characteristics section.  
21. tR applies only in the Deep Sleep Mode.  
22. H = VIH, L = VIL, X = Don’t Care.  
Document #: 38-05454 Rev. **  
Page 8 of 10  
ADVANCE  
INFORMATION  
CYK001M16ZCCAU  
MoBL3™  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
CYK001M16ZCCAU-70BAI  
Package Type  
70  
BA48K 48-ball Fine Pitch BGA (6.0 x 8.0 x 1.2 mm)  
Industrial  
Package Diagrams  
48-Ball (6 mm x 8 mm x 1.2 mm) FBGA BA48K  
BOTTOM VIEW  
TOP VIEW  
A1 CORNER  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05ꢀ(48X  
A1 CORNER  
1
2
3
5
6
6
5
3
2
1
(
(
A
B
A
B
C
C
D
D
E
F
E
F
G
H
G
H
1.475  
A
A
0.75  
3.75  
6.00 0.10  
B
6.00 0.10  
B
0.15ꢀ(8X  
REFERENCE JEDEC MO-207  
SEATING PLANE  
C
51-85193-*A  
MoBL is a registered trademark, and MoBL3 and More Battery Life are trademarks, of Cypress Semiconductor. All product and  
company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05454 Rev. **  
Page 9 of 10  
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
ADVANCE  
INFORMATION  
CYK001M16ZCCAU  
MoBL3™  
Document History Page  
Document Title: CYK001M16ZCCAU 16-Mb (1Mb x 16) Pseudo Static RAM  
Document Number: 38- 05454  
Orig. of  
REV.  
ECN NO. Issue Date Change  
Description of Change  
New Data Sheet  
**  
132407 01/27/2004  
AWK  
Document #: 38-05454 Rev. **  
Page 10 of 10  
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