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TZA3057HW

型号：

TZA3057HW

品牌：

NXP[ NXP ]

页数：

23 页

PDF大小：

120 K

下载PDF手册
INTEGRATED CIRCUITS  
DATA SHEET  
TZA3057HW  
SDH/SONET, Fibre Channel and  
Gigabit Ethernet multi-rate fibre  
optic transmitter  
Product specification  
2003 Nov 07  
Supersedes data of 2002 Aug 15  
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
FEATURES  
APPLICATIONS  
• A-rateTM(1) technology supports all bit rates from the  
• SDH/SONET, Fibre Channel and Gigabit Ethernet  
same reference frequency  
optical transmission systems  
• Supports eight bit rates:  
• Physical interface IC in transmit channels  
• Transponder applications  
– SDH/SONET rates at 155.52 Mbits/s,  
622.08 Mbits/s, 2488.32 Mbits/s and  
2666.06 Mbits/s (STM16/OC48 + FEC)  
• Dense Wavelength Division Multiplexing (DWDM)  
systems.  
– Fibre Channel at 1062.5 Mbits/s and 2125 Mbits/s  
– Gigabit Ethernet at 1250 Mbits/s and 3125 Mbits/s  
• 4-stage FIFO for wide tolerance to clock skew  
• Loss Of Lock (LOL) indicator  
GENERAL DESCRIPTION  
The TZA3057HW is a fully integrated optical network  
transmitter, containing an A-rate clock synthesizer core,  
supporting all line rates from one single reference  
frequency and a programmable multiplexer, supporting  
16 : 1, 10 : 1, 8 : 1 or 4 : 1 multiplexing ratios. The  
transmitter supports diagnostic and line loopback modes.  
• ITU-T compliant jitter generation  
• CML data and clock outputs, and loop mode inputs  
• Line loopback input  
• Diagnostic loopback output  
• 16 : 1, 10 : 1, 8 : 1 or 4 : 1 multiplexing ratio  
• Rail-to-rail parallel inputs compliant with LVPECL, CML  
and LVDS  
• Supports co-directional and contra-directional clocking  
• Programmable parity checking  
• Temperature alarm  
• Pin compatible with continuous rate TZA3017HW  
transmitter chip  
• Single 3.3 V power supply.  
(1) A-rate is a trademark of Koninklijke Philips Electronics N.V.  
ORDERING INFORMATION  
TYPE  
PACKAGE  
NUMBER  
NAME  
DESCRIPTION  
VERSION  
TZA3057HW  
HTQFP100  
plastic thermal enhanced thin quad flat package; 100 leads;  
SOT638-1  
body 14 × 14 × 1.0 mm; exposed die pad  
2003 Nov 07  
2
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  a
DIN  
MUXR1  
MUXR0 CINQ  
CIN  
DINQ  
46 45 81 82 78 79  
55  
56  
74  
73  
44  
OVERFLOW  
FIFORESET  
PARERR  
84  
TEMPERATURE  
ALARM  
TEMPAL  
PARERRQ  
PAREVEN  
D
C
67  
66  
38  
37  
DOUT  
2
2
PARITY  
DOUTQ  
PARITYQ  
16  
60  
59  
D00 to D15  
COUT  
PARITY  
CHECKER  
4, 6, 8, 10, 12, 15, 17,  
19, 21, 23, 28, 30, 32,  
95, 97, 99  
MUX  
2
16  
16  
16  
16  
COUTQ  
D
C
4 : 1  
4 deep  
FIFO  
8 : 1  
2
10 : 1  
16 : 1  
16  
D00Q to D15Q  
89  
88  
DLOOP  
2
2
3, 5, 7, 9, 11, 14, 16,  
18, 20, 22, 27, 29, 31,  
94, 96, 98  
W
R
DLOOPQ  
92  
91  
35  
34  
CLOOP  
PICLK  
CLOOPQ  
PICLKQ  
85  
86  
TZA3057HW  
ENLOUTQ  
ENLINQ  
72  
n.c.  
POWER-ON  
RESET  
CLOCK  
SYNTHESIZER  
54  
53  
52  
DR0  
DR1  
DR2  
71  
40  
39  
LINE RATE  
SELECT  
CLKDIR  
POCLK  
1, 25, 33, 36, 41, 49,  
58, 61, 64, 65, 68, 77,  
80, 83, 87, 90, 93, 100  
POCLKQ  
2, 13, 24,  
26, 50,  
70, 76  
62  
63  
57 48 47 43 42  
75  
69  
51  
MGU708  
18  
7
V
V
V
V
V
EE  
MD0 MD1  
PRSCLO CREF  
CCD CCA CCO  
DD  
LOL PRSCLOQ CREFQ  
Fig.1 Block diagram.  
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
PINNING  
SYMBOL  
D00  
PIN  
DESCRIPTION  
SYMBOL  
VEE  
PIN  
DESCRIPTION  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
parallel data input 00  
die  
pad  
common ground plane  
VCCD  
supply voltage (digital part)  
parallel clock input inverted  
parallel clock input  
PICLKQ  
PICLK  
VCCD  
VCCD  
VEE  
1
supply voltage (digital part)  
ground  
2
supply voltage (digital part)  
parity input inverted  
D12Q  
D12  
3
parallel data input 12 inverted  
parallel data input 12  
PARITYQ  
PARITY  
POCLKQ  
POCLK  
VCCD  
4
parity input  
D11Q  
D11  
5
parallel data input 11 inverted  
parallel data input 11  
parallel clock output inverted  
parallel clock output  
6
D10Q  
D10  
7
parallel data input 10 inverted  
parallel data input 10  
supply voltage (digital part)  
reference clock input inverted  
reference clock input  
8
CREFQ  
CREF  
D09Q  
D09  
9
parallel data input 09 inverted  
parallel data input 09  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
PAREVEN  
MUXR1  
MUXR0  
PRSCLOQ  
PRSCLO  
VCCD  
parity select (odd or even)  
multiplexer ratio select 1 input  
multiplexer ratio select 0 input  
prescaler output signal inverted  
prescaler output signal  
supply voltage (digital part)  
ground  
D08Q  
D08  
parallel data input 08 inverted  
parallel data input 08  
VEE  
ground  
D07Q  
D07  
parallel data input 07 inverted  
parallel data input 07  
D06Q  
D06  
parallel data input 06 inverted  
parallel data input 06  
VEE  
VDD  
supply voltage (digital part)  
data rate select 2 input  
data rate select 1 input  
data rate select 0 input  
FIFO overflow alarm output  
FIFO reset input  
D05Q  
D05  
parallel data input 05 inverted  
parallel data input 05  
DR2  
DR1  
D04Q  
D04  
parallel data input 04 inverted  
parallel data input 04  
DR0  
OVERFLOW  
FIFORESET  
LOL  
D03Q  
D03  
parallel data input 03 inverted  
parallel data input 03  
loss of lock output  
VEE  
ground  
VCCD  
supply voltage (digital part)  
serial clock output inverted  
serial clock output  
VCCD  
VEE  
supply voltage (digital part)  
ground  
COUTQ  
COUT  
D02Q  
D02  
parallel data input 02 inverted  
parallel data input 02  
VCCD  
supply voltage (digital part)  
MD0  
parallel data input termination  
mode select 0  
D01Q  
D01  
parallel data input 01 inverted  
parallel data input 01  
MD1  
63  
parallel data input termination  
mode select 1  
D00Q  
parallel data input 00 inverted  
2003 Nov 07  
4
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
SYMBOL  
VCCD  
PIN  
DESCRIPTION  
SYMBOL  
VCCD  
PIN  
DESCRIPTION  
64  
65  
66  
67  
68  
69  
70  
71  
supply voltage (digital part)  
supply voltage (digital part)  
serial data output inverted  
serial data output  
83  
84  
85  
supply voltage (digital part)  
temperature alarm output  
VCCD  
TEMPAL  
DOUTQ  
DOUT  
VCCD  
ENLOUTQ  
diagnostic loopback enable  
input (active LOW)  
ENLINQ  
86  
line loopback enable input  
(active LOW)  
supply voltage (digital part)  
supply voltage (clock generator)  
ground  
VCCO  
VCCD  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
supply voltage (digital part)  
loop mode data output inverted  
loop mode data output  
VEE  
DLOOPQ  
DLOOP  
VCCD  
CLKDIR  
selection between co- and  
contra-directional clocking  
supply voltage (digital part)  
loop mode clock output inverted  
loop mode clock output  
n.c.  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
not connected  
CLOOPQ  
CLOOP  
VCCD  
PARERRQ  
PARERR  
VCCA  
parity error output inverted  
parity error output  
supply voltage (digital part)  
parallel data input 15 inverted  
parallel data input 15  
supply voltage (analog part)  
ground  
D15Q  
D15  
VEE  
VCCD  
DINQ  
DIN  
supply voltage (digital part)  
loop mode data input inverted  
loop mode data input  
supply voltage (digital part)  
loop mode clock input inverted  
loop mode clock input  
D14Q  
D14  
parallel data input 14 inverted  
parallel data input 14  
D13Q  
D13  
parallel data input 13 inverted  
parallel data input 13  
VCCD  
CINQ  
CIN  
VCCD  
100 supply voltage (digital part)  
2003 Nov 07  
5
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
V
V
1
2
75  
CCD  
CCA  
V
74 PARERR  
EE  
D12Q  
D12  
3
PARERRQ  
n.c.  
73  
72  
71  
70  
69  
68  
4
CLKDIR  
D11Q  
D11  
5
6
V
EE  
D10Q  
D10  
V
7
CCO  
V
8
CCD  
D09Q  
D09  
9
67 DOUT  
10  
66 DOUTQ  
D08Q 11  
V
V
65  
64  
CCD  
CCD  
D08  
12  
13  
V
TZA3057HW  
63 MD1  
EE  
D07Q 14  
D07 15  
MD0  
V
62  
61  
CCD  
16  
D06Q  
D06 17  
18  
60 COUT  
59  
58  
57  
COUTQ  
V
D05Q  
D05 19  
CCD  
LOL  
20  
21  
22  
23  
24  
25  
D04Q  
D04  
56 FIFORESET  
55 OVERFLOW  
DR0  
DR1  
D03Q  
D03  
54  
53  
V
52 DR2  
EE  
V
V
DD  
51  
CCD  
MGU709  
Fig.2 Pin configuration.  
2003 Nov 07  
6
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
FUNCTIONAL DESCRIPTION  
Clock synthesizer  
The TZA3057HW converts parallel input data into serial  
output data with a bit rate of 155 Mbits/s to 3.1 Gbits/s (see  
Table 1). An internal clock synthesizer synchronizes the  
internal oscillator to an external reference frequency. The  
parallel input data is multiplexed at a ratio of 16 : 1, 10 : 1,  
8 : 1 or 4 : 1.  
Refer to Fig.3. The clock synthesizer consists of a Voltage  
Controlled Oscillator (VCO), main divider, Phase  
Frequency Detector (PFD), integrated loop filter, Loss Of  
Lock (LOL) detection circuit and a prescaler output buffer.  
The internal VCO is phase-locked to a reference clock  
signal of typically 19.44 MHz applied to pins CREF and  
CREFQ.  
Configuring the TZA3057HW using pins DR2 to DR0  
The clock synthesizer does not require any external  
components, allowing easier application use.  
The IC supports eight bit rates using an external reference  
clock frequency of 19.44 MHz. Pins DR2 to DR0 are  
standard CMOS inputs that select one of the eight  
pre-programmed bit rates using one external reference  
clock frequency of 19.44 MHz (see Table 1).  
To comply with most transmission standards, the  
reference frequency must be very accurate with minimum  
phase noise in order to synthesize a pure RF clock signal  
that complies with the strictest requirements for jitter  
generation; see Section “Jitter performance”.  
Table 1 Truth table for pin DR  
Prescaler outputs  
BIT RATE  
(Mbits/s)  
DR2  
DR1  
DR0  
PROTOCOL  
The frequency of prescaler outputs PRSCLO and  
PRSCLOQ is the VCO frequency divided by the main  
division factor. If the synthesizer is in-lock, the frequency  
of the prescaler output is equal to the reference frequency  
at CREF and CREFQ. This provides an accurate  
reference that can be used by other phase lock loops in the  
application.  
LOW  
LOW  
LOW  
LOW STM1/OC3  
155.52  
622.08  
LOW HIGH STM4/OC12  
LOW HIGH LOW STM16/OC48  
LOW HIGH HIGH STM16 + FEC  
2488.32  
2666.06  
1250.00  
3125.00  
1062.50  
2125.00  
HIGH LOW  
LOW GE  
HIGH LOW HIGH 10GE  
Loss of lock  
HIGH HIGH LOW Fibre Channel  
HIGH HIGH HIGH Fibre Channel  
During normal operation, pin LOL should be LOW to  
indicate that the clock synthesizer is in-lock and that the  
output frequency corresponds to the programmed value.  
If pin LOL goes HIGH, phase and/or frequency lock is lost  
and the output frequency may deviate from the  
programmed value.  
LOL  
CREF(Q)  
up  
VCO  
PHASE-  
CHARGE PUMP  
to  
FREQUENCY  
DETECTOR  
AND  
down  
MUX  
LOOP FILTER  
MAIN  
DIVIDER  
MGU710  
PRSCLO(Q)  
DR  
Fig.3 Functional diagram of the clock synthesizer.  
7
2003 Nov 07  
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
Jitter performance  
Multiplexer  
The clock synthesizer is optimized for minimum jitter  
generation. For all SDH/SONET bit rates, the generated  
jitter complies with ITU-T standard G.958, using a pure  
reference clock. To ensure negligible loss of performance,  
the reference signal should have a single sideband phase  
noise of better than −140 dBc/Hz, at frequencies of more  
than 12 kHz from the carrier.  
The multiplexer comprises a high-speed input register, a  
4-bit deep First In First Out (FIFO) elastic buffer, a parity  
check circuit and a multiplexing tree.  
Parallel input bus clocking schemes  
The TZA3057HW supports both co-directional and  
contra-directional clocking schemes for the parallel data  
bus (see Figs 5 and 6). The clocking scheme is selected  
by pin CLKDIR. Co-directional clocking is the default  
setting and is selected when pin CLKDIR is HIGH. With  
co-directional clocking selected, the incoming clock is  
applied to pins PICLK and PICLKQ and the input data is  
applied to pins D00 to D00Q and D15 to D15Q. A parallel  
output clock is available at pins POCLK and POCLKQ.  
Reference input  
For optimum jitter performance and Power Supply  
Rejection Ratio (PSRR), the sensitive reference input  
should be driven differentially. If the reference frequency  
source (fref) is single-ended, the unused CREF or CREFQ  
input should be terminated with an impedance which  
matches the source impedance Rsource (see Fig.4).  
The PSRR can be improved by AC coupling the reference  
frequency source to inputs CREF and CREFQ. Any low  
frequency noise injected from the fref power supply will be  
attenuated by the resulting high-pass filter. The low cut-off  
frequency of the AC coupling must be lower than the  
reference frequency, otherwise the reference signal will be  
attenuated and the signal to noise ratio will be made  
worse. The value of coupling capacitor C is calculated  
When contra-directional clocking is selected, any incoming  
clock at pins PICLK and PICLKQ is not used.  
In contra-directional clocking mode, the incoming data on  
the parallel data bus is sampled by the internally generated  
parallel output clock. In this mode, the parallel data source  
must be clocked using the parallel output clock signal at  
pins POCLK and POCLKQ.  
1
using the formula: C >  
-----------------------------------  
2πRsourcefref  
V
handbook, halfpage  
CCD  
V
CC  
50 Ω  
50 Ω  
43 CREF  
42 CREFQ  
C
C
R
R
source  
source  
f
ref  
on-chip off-chip  
MDB060  
Fig.4 Reference input with single-ended clock  
source.  
2003 Nov 07  
8
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
FRAMER  
TZA3057HW  
PARITY  
TX_PARITY  
PARITYQ  
16  
16  
D00 to D15  
D00Q to D15Q  
PICLK  
TX_DATA  
TX_CLK  
PICLKQ  
POCLK  
TX_CLK_SRC  
POCLKQ  
FIFORESET CREF  
MGU711  
system  
clock  
Fig.5 Co-directional clocking diagram.  
FRAMER  
TZA3057HW  
PARITY  
TX_PARITY  
TX_DATA  
PARITYQ  
16  
16  
D00 to D15  
D00Q to D15Q  
POCLK  
TX_CLK_SRC  
POCLKQ  
FIFORESET CREF  
MGU712  
system  
clock  
Fig.6 Contra-directional clocking diagram.  
9
2003 Nov 07  
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
FIFO  
multiplexing ratio selected by pins MUXR0 and MUXR1.  
Any unused parallel data bus inputs are disabled. The  
configuration settings and active inputs for each  
multiplexing ratio are shown in table 2. The highest  
supported speed for the parallel data bus is 400 Mbits/s.  
Therefore the multiplexing ratio of 4 : 1 will only support  
the following bit rates: 155 Mbits/s, 622 Mbits/s,  
1062.5 Mbits/s (FC) and 1250 Mbits/s (GE).  
In the co-directional clocking scheme, the FIFO input  
register samples the incoming parallel data on the rising  
edge of the clock signal at pins PICLK and PICLKQ. Data  
is retrieved from the FIFO by an internal clock, derived  
from the multiplexing tree clock generator. This provides a  
high tolerance to jitter, or clock skew, at inputs on the  
parallel interface. The FIFO can compensate for brief  
phase deviations, or clock skew, of up to plus or minus  
1 unit interval. Large phase deviations will most likely  
cause the FIFO to either overflow or underflow, and is  
Table 2 Setting the multiplexing ratio  
PIN  
PIN  
MULTIPLEX ACTIVE OUTPUTS  
indicated by a HIGH level at pin OVERFLOW.  
DMXR1 DMXR0  
RATIO  
LSB TO MSB  
LOW  
LOW  
HIGH  
HIGH  
LOW  
HIGH  
LOW  
HIGH  
4 : 1  
8 : 1  
D06 to D09  
D04 to D11  
D03 to D12  
D00 to D15  
The overflow condition exists until the FIFO is reset by a  
HIGH level on pin FIFORESET. FIFORESET also  
initializes the FIFO. For optimum performance, the FIFO  
should be reset whenever there has been a loss of lock  
condition, or whenever the bit rate is changed.  
10 : 1  
16 : 1  
The FIFORESET signal is re-timed by the internal clock  
generator signal. The FIFO will initialize two clock cycles  
after FIFORESET goes HIGH and is operational two clock  
cycles after FIFORESET goes LOW. The FIFO can be  
initialized automatically when an overflow occurs by  
connecting pin OVERFLOW to pin FIFORESET.  
Parity checking  
The parity checking function verifies the integrity of the  
incoming data on the parallel data bus. The calculated  
parity is compared to the parity expected at pins PARITY  
and PARITYQ. If these levels do not match, a parity error  
has occurred and pin PARERR goes HIGH during the next  
parallel clock period at pins PICLK and PICLKQ (see  
Fig.7).  
Adjustable multiplexing ratio  
For optimum layout connectivity, the physical positions of  
parallel data bus pins D00(Q) to D15(Q) on the chip are  
located on either side of pin VEE (pin 13). The number of  
parallel data bus inputs that are used depends on the  
The calculated parity can be configured to be either odd or  
even by pin PAREVEN. Odd parity is configured by a LOW  
level at pin PAREVEN.  
PICLK  
D00-D15  
PARITY  
PARERR  
PARITY  
ERROR  
MDB063  
Fig.7 Parity timing.  
2003 Nov 07  
10  
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
Rail-to-rail parallel data and clock inputs  
Table 3 Input termination mode selection  
The differential parallel data, parity and clock inputs, D00  
to D15, D00Q to D15Q, PARITY, PARITYQ, PICLK and  
PICLKQ can handle input swings from 100 mV,  
single-ended, to a maximum of 1000 mV. These rail-to-rail  
inputs can also accept any absolute value between VEE  
INPUT  
MODE  
PIN MD1 PIN MD0  
TERMINATION  
LOW  
LOW  
LOW  
floating  
LVDS  
100 Ω differential  
HIGH  
100 Ω differential  
(hysteresis on)  
and VCC  
.
HIGH  
HIGH  
LOW  
CML  
50 Ω to VCC  
To keep the number of external components required to a  
minimum, most of the common standards: LVPECL, CML  
and LVDS are terminated internally (see Fig.8).  
HIGH  
LVPECL  
50 Ω to VCC − 2 V  
The LVDS mode has a differential hysteresis of 30 mV  
implemented by default.  
The termination mode is determined by pins MD0 and  
MD1; see Table 3.  
V
V
CCD  
CCD  
V
CCD  
2 V  
D
D
D
50 Ω  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
50 Ω  
DQ  
DQ  
DQ  
V
EE  
V
V
EE  
CML termination  
EE  
Floating and LVDS termination  
LVPECL termination  
MDB062  
Fig.8 Rail-to-rail input termination configurations.  
Loop mode I/Os  
CMOS control inputs  
In line loopback mode, the internal data and clock routing  
switch selects serial data and clock signals from input pins  
DIN, DINQ, CIN and CINQ instead of from the output of the  
multiplexer. Line loopback mode is activated by a LOW  
level on pin ENLINQ.  
CMOS control input pins DR0, DR1, DR2, MUXR0,  
MUXR1, PAREVEN, CLKDIR, ENLOUTQ, ENLINQ, MD0,  
MD1 and FIFORESET have an internal pull-up resistor so  
that these pins go HIGH when open circuit and go LOW  
when deliberately forced.  
In diagnostic loopback mode, the synthesized serial data  
and clock signals are available at loop mode output pins  
DLOOP, DLOOPQ, CLOOP and CLOOPQ and at output  
pins DOUT, DOUTQ, COUT and COUTQ. Diagnostic  
loopback mode is activated when pin ENLOUTQ is LOW.  
Temperature alarm  
The TZA3057HW features a temperature alarm. The  
temperature alarm switches the open-drain output of pin  
TEMPAL to LOW at a junction temperature above 130 oC.  
The CML RF outputs have an amplitude of 280 mV (p-p),  
single-ended (when DC-coupled in the application).  
2003 Nov 07  
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Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
Power supply connections  
main ground return of the IC, this connection must also  
have a low DC impedance. The voltage supply levels  
should be in accordance with the values specified in  
Chapters “Limiting values” and “Characteristics”.  
Four separate supply domains (VDD, VCCD, VCCO and  
VCCA) provide isolation between the various functional  
blocks. Each supply domain should be connected to a  
common VCC using a separate filter. All supply pins,  
including the exposed die pad, must be connected.  
The die pad connection to ground must have the lowest  
possible inductance. Since the die pad is also used as the  
All external components should be surface mounted, with  
a preferable size of 0603 or smaller. The components  
must be mounted as close to the IC as possible.  
LIMITING VALUES  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
SYMBOL PARAMETER  
MIN.  
−0.5  
MAX.  
+3.6  
UNIT  
VCCD, VCCA, supply voltages  
V
VCCO,VDD  
Vn  
DC voltage on pins  
D00 to D15, D00Q to D15Q, PICLK, PICLKQ, PARITY and PARITYQ VCC − 0.5 VCC + 0.5  
V
V
V
POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO and PRSCLOQ  
VCC − 2.5 VCC + 0.5  
DR0, DR1, DR2, CLKDIR, PAREVEN, FIFORESET, MD0, MD1,  
ENLOUTQ and ENLINQ  
−0.5  
VCC + 0.5  
LOL and OVERFLOW  
TEMPAL  
−0.5  
−0.5  
VCC + 0.5  
CC + 0.5  
V
V
V
In  
input current on pins  
D00 to D15, D00Q to D15Q, PICLK, PICLKQ, PARITY and PARITYQ −25  
+25  
+20  
+2  
mA  
mA  
mA  
°C  
CREF, CREFQ, CIN, CINQ, DIN and DINQ  
TEMPAL  
−20  
−2  
Tamb  
Tj  
ambient temperature  
−40  
−
+85  
125  
+150  
junction temperature  
°C  
Tstg  
storage temperature  
−65  
°C  
THERMAL CHARACTERISTICS  
SYMBOL  
PARAMETER  
thermal resistance from junction to ambient  
CONDITIONS  
notes 1 and 2  
VALUE  
UNIT  
Rth(j-a)  
16  
K/W  
Notes  
1. In compliance with JEDEC standards JESD51-5 and JESD51-7.  
2. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and  
fourth ground layer in the PCB.  
2003 Nov 07  
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Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
CHARACTERISTICS  
VCC = 3.14 to 3.47 V; Tamb = −40 to +85 °C; Rth(j-a) ≤ 16 K/W; all voltages are referenced to ground; positive currents  
flow into the device; unless otherwise specified.  
SYMBOL  
Supplies  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
ICCA  
ICCD  
IDD  
analog supply current  
digital supply current  
digital supply current  
oscillator supply current  
total supply current  
0.5  
170  
0
1.2  
2.4  
mA  
mA  
mA  
mA  
mA  
W
note 1  
215  
2
270  
4
ICCO  
ICC(tot)  
Ptot  
20  
31  
41  
note 1  
note 1  
190  
0.6  
250  
0.82  
318  
1.1  
total power dissipation  
CMOS input: pins DR0, DR1, DR2, MD0, MD1, ENLINQ, ENLOUTQ, FIFORESET, PAREVEN and CLKDIR  
VIL  
VIH  
IIL  
LOW-level input voltage  
HIGH-level input voltage  
LOW-level input current  
HIGH-level input current  
−
−
−
−
−
0.2VCC  
V
0.8VCC  
−200  
−
−
V
VIL = 0 V  
VIH = VCC  
−
µA  
µA  
IIH  
10  
CMOS output: pins OVERFLOW and LOL  
VOL  
VOH  
LOW-level output voltage  
IOL = 1 mA  
0
−
−
0.2  
V
V
HIGH-level output voltage IOH = −0.5 mA  
V
CC − 0.2  
VCC  
Open-drain output: pin TEMPAL  
VOL  
IOH  
LOW-level output voltage  
HIGH-level output current  
IOL = 1 mA  
VOH = VCC  
0
−
−
0.2  
10  
V
−
µA  
Serial output: pins COUT, COUTQ, DOUT, DOUTQ, CLOOP, CLOOPQ, DLOOP and DLOOPQ  
Vo(p-p)  
output voltage swing  
(peak-to-peak value)  
single-ended with 50 Ω  
external load  
220  
280  
340  
mV  
VO  
Zo  
tr  
DC output voltage  
output impedance  
rise time  
V
CC − 2  
−
VCC  
60  
V
single-ended to VCC  
20% to 80%  
40  
−
50  
60  
60  
−
Ω
90  
ps  
ps  
ps  
tf  
fall time  
80% to 20%  
−
90  
tD-C  
data-to-clock delay  
between differential  
−50  
+50  
crossovers; see Fig.13  
δ
duty cycle COUT and  
COUTQ  
between differential  
crossovers  
40  
50  
50  
60  
%
Serial input: pins DIN, DINQ, CIN and CINQ  
Vi(p-p)  
input voltage  
single-ended  
−
1000  
mV  
(peak-to-peak value)  
Vi  
Zi  
input voltage  
V
CC − 1  
−
VCC + 0.25  
60  
V
input impedance  
single-ended to VCC  
40  
50  
Ω
2003 Nov 07  
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Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Parallel input (rail-to-rail): pins D00 to D15, D00Q to D15Q, PARITY, PARITYQ, PICLK and PICLKQ  
Vi  
input voltage  
V
EE − 0.25  
−
−
VCC + 0.25  
1000  
V
Vi(p-p)  
input voltage swing  
(peak-to-peak value)  
single-ended  
100  
mV  
mV  
Ω
Vi(hys)  
Zi(dif)  
input differential hysteresis MD1 = LOW;  
voltage  
−
30  
−
MD0 = HIGH  
differential input  
impedance  
MD1 = LOW  
80  
40  
−
100  
50  
120  
60  
−
Zi(se)  
single-ended input  
impedance  
MD1 = HIGH  
Ω
VT(CML)  
VT(LVPECL)  
tsu(co)  
th(co)  
input termination voltage in MD1 = HIGH;  
CML mode MD0 = LOW  
input termination voltage in MD1 = HIGH;  
VCC  
V
V
CC − 2.3  
V
CC − 2  
V
−
−
−
−
CC − 1.7  
V
LVPECL mode  
MD0 = HIGH  
co-directional clocking  
set-up time  
see Fig.11  
0
−
ps  
ps  
ps  
ps  
%
co-directional clocking hold see Fig.11  
time  
1000  
1300  
−300  
40  
−
tsu(contra)  
th(contra)  
δ
contra-directional clocking see Fig.12  
set-up time  
−
contra-directional clocking see Fig.12  
hold time  
−
duty cycle PICLK and  
PICLKQ  
between differential  
crossovers  
50  
60  
LVPECL output: pins POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO and PRSCLOQ  
VOH  
HIGH-level output voltage 50 Ω termination to  
CC − 2V  
50 Ω termination to  
CC − 2V  
V
CC − 1.2  
V
CC − 1.0  
V
CC − 0.9  
CC − 1.7  
V
V
V
VOL  
LOW-level output voltage  
V
CC − 2.2  
VCC − 1.9  
V
V
tr  
tf  
rise time  
fall time  
20% to 80%  
80% to 20%  
300  
300  
350  
350  
400  
400  
ps  
ps  
Reference frequency input: pins CREF and CREFQ  
Vi(p-p)  
input voltage  
single-ended  
50  
−
1000  
mV  
(peak-to-peak value)  
VI  
DC input voltage  
input impedance  
V
CC − 1  
−
VCC + 0.25  
60  
V
Zi  
single-ended to VCC  
40  
−20  
50  
−
Ω
∆fCREF  
reference clock frequency SDH/SONET  
accuracy requirement  
+20  
ppm  
2003 Nov 07  
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Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN.  
TYP.  
MAX.  
UNIT  
Jitter generation  
Jgen(p-p)  
jitter generation  
(peak-to-peak value)  
STM16/OC3 mode;  
note 2  
f = 500 Hz to 1.3 MHz  
f = 12 kHz to 1.3 MHz  
f = 65 kHz to 1.3 MHz  
−
−
−
−
−
−
0.016  
UI  
0.016  
0.004  
UI  
UI  
STM16/OC12 mode;  
note 2  
f = 1 kHz to 5 MHz  
f = 12 kHz to 5 MHz  
f = 250 kHz to 5 MHz  
−
−
−
−
−
−
0.063  
0.063  
0.013  
UI  
UI  
UI  
STM16/OC48 mode;  
note 2  
f = 5 kHz to 20 MHz  
f = 12 kHz to 20 MHz  
f = 1 MHz to 20 MHz  
−
−
−
0.035  
0.032  
0.007  
0.250  
0.050  
0.050  
UI  
UI  
UI  
Notes  
1. Default settings: DR = LOW (STM16/OC48); PAREVEN = HIGH (even parity); FIFORESET = LOW; MD0 = LOW,  
MD1 = LOW (100 Ω differential); CLKDIR = HIGH (co-directional clocking); ENLOUTQ = HIGH (DLOOP, DLOOPQ,  
CLOOP and CLOOPQ disabled); ENLINQ = HIGH (DIN, DINQ, CIN and CINQ disabled); CREF and  
CREFQ = 19.44 MHz; COUT, COUTQ, DOUT, DOUTQ, POCLK, POCLKQ, PARERR, PARERRQ, PRSCLO and  
PRSLOQ are not connected.  
2. Reference frequency of 19.44 MHz with a phase noise of less than −140 dBc for frequencies of more than 12 kHz  
from the carrier. Measured for 60 seconds within the appropriate bandwidth.  
2003 Nov 07  
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Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
SWING CONTROL  
V
CC  
V
2 V  
term  
optional  
AC coupling  
transmission  
lines  
OUT  
to high-  
impedance  
input  
50 Ω  
50 Ω  
OUTQ  
I
swing  
50 Ω  
50 Ω  
in  
on-chip  
off-chip  
MBL562  
Fig.9 Parallel output standard LVPECL mode.  
SWING CONTROL  
V
CC  
50 Ω  
50 Ω  
50 Ω  
transmission  
50 Ω  
lines  
OUT  
to high-  
impedance  
input  
50 Ω  
50 Ω  
OUTQ  
I
swing  
in  
on-chip  
off-chip  
MDB069  
Fig.10 Serial output CML mode (DC-coupled).  
16  
2003 Nov 07  
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
PICLK  
t
h(co)  
t
su(co)  
D00 to D15,  
PARITY  
valid data  
POCLK  
MBL581  
The timing is measured from the crossover point of the reference signal to the crossover point of the input.  
Fig.11 Parallel bus co-directional timing.  
D00 to D15,  
valid data  
PARITY  
t
su(contra)  
t
h(contra)  
POCLK  
MBL582  
The timing is measured from the crossover point of the reference signal to the crossover point of the input.  
Fig.12 Parallel bus contra-directional timing.  
2003 Nov 07  
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Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
COUT, CLOOP  
t
D-C  
DOUT, DLOOP  
MBL583  
The timing is measured from the crossover point of the reference signal to the crossover point of the output.  
Fig.13 RF output timing.  
2003 Nov 07  
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Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
PACKAGE OUTLINE  
HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads;  
body 14 x 14 x 1 mm; exposed die pad  
SOT638-1  
c
y
exposed die pad side  
X
D
h
A
75  
51  
50  
76  
Z
E
e
H
E
E
E
(A )  
3
A
h
2
A
A
1
w
p
M
θ
b
L
p
pin 1 index  
L
detail X  
26  
100  
1
25  
w
M
Z
v
M
A
B
D
b
p
e
D
B
H
v
M
D
0
10 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
A
(1)  
(1)  
(1)  
(1)  
UNIT  
A
A
A
b
c
D
D
E
E
e
H
H
L
L
p
v
w
y
Z
Z
E
θ
1
2
3
p
h
h
D
E
D
max.  
0.15 1.05  
0.05 0.95  
0.27 0.20 14.1 7.1 14.1 7.1  
0.17 0.09 13.9 6.1 13.9 6.1  
16.15 16.15  
15.85 15.85  
0.75  
0.45  
1.15 1.15  
0.85 0.85  
7°  
0°  
mm  
1.2  
0.25  
0.5  
1
0.2 0.08 0.08  
Note  
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
01-03-30  
03-04-07  
SOT638-1  
2003 Nov 07  
19  
Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
SOLDERING  
To overcome these problems the double-wave soldering  
method was specifically developed.  
Introduction to soldering surface mount packages  
If wave soldering is used the following conditions must be  
observed for optimal results:  
This text gives a very brief insight to a complex technology.  
A more in-depth account of soldering ICs can be found in  
our “Data Handbook IC26; Integrated Circuit Packages”  
(document order number 9398 652 90011).  
• Use a double-wave soldering method comprising a  
turbulent wave with high upward pressure followed by a  
smooth laminar wave.  
There is no soldering method that is ideal for all surface  
mount IC packages. Wave soldering can still be used for  
certain surface mount ICs, but it is not suitable for fine pitch  
SMDs. In these situations reflow soldering is  
recommended.  
• For packages with leads on two sides and a pitch (e):  
– larger than or equal to 1.27 mm, the footprint  
longitudinal axis is preferred to be parallel to the  
transport direction of the printed-circuit board;  
– smaller than 1.27 mm, the footprint longitudinal axis  
must be parallel to the transport direction of the  
printed-circuit board.  
Reflow soldering  
Reflow soldering requires solder paste (a suspension of  
fine solder particles, flux and binding agent) to be applied  
to the printed-circuit board by screen printing, stencilling or  
pressure-syringe dispensing before package placement.  
Driven by legislation and environmental forces the  
The footprint must incorporate solder thieves at the  
downstream end.  
• For packages with leads on four sides, the footprint must  
be placed at a 45° angle to the transport direction of the  
printed-circuit board. The footprint must incorporate  
solder thieves downstream and at the side corners.  
worldwide use of lead-free solder pastes is increasing.  
Several methods exist for reflowing; for example,  
convection or convection/infrared heating in a conveyor  
type oven. Throughput times (preheating, soldering and  
cooling) vary between 100 and 200 seconds depending  
on heating method.  
During placement and before soldering, the package must  
be fixed with a droplet of adhesive. The adhesive can be  
applied by screen printing, pin transfer or syringe  
dispensing. The package can be soldered after the  
adhesive is cured.  
Typical reflow peak temperatures range from  
215 to 270 °C depending on solder paste material. The  
top-surface temperature of the packages should  
preferably be kept:  
Typical dwell time of the leads in the wave ranges from  
3 to 4 seconds at 250 °C or 265 °C, depending on solder  
material applied, SnPb or Pb-free respectively.  
• below 220 °C (SnPb process) or below 245 °C (Pb-free  
process)  
A mildly-activated flux will eliminate the need for removal  
of corrosive residues in most applications.  
– for all BGA and SSOP-T packages  
Manual soldering  
– for packages with a thickness ≥ 2.5 mm  
– for packages with a thickness < 2.5 mm and a  
Fix the component by first soldering two  
diagonally-opposite end leads. Use a low voltage (24 V or  
less) soldering iron applied to the flat part of the lead.  
Contact time must be limited to 10 seconds at up to  
300 °C.  
volume ≥ 350 mm3 so called thick/large packages.  
• below 235 °C (SnPb process) or below 260 °C (Pb-free  
process) for packages with a thickness < 2.5 mm and a  
volume < 350 mm3 so called small/thin packages.  
When using a dedicated tool, all other leads can be  
soldered in one operation within 2 to 5 seconds between  
270 and 320 °C.  
Moisture sensitivity precautions, as indicated on packing,  
must be respected at all times.  
Wave soldering  
Conventional single wave soldering is not recommended  
for surface mount devices (SMDs) or printed-circuit boards  
with a high component density, as solder bridging and  
non-wetting can present major problems.  
2003 Nov 07  
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Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
Suitability of surface mount IC packages for wave and reflow soldering methods  
SOLDERING METHOD  
PACKAGE(1)  
WAVE  
not suitable  
REFLOW(2)  
BGA, LBGA, LFBGA, SQFP, SSOP-T(3), TFBGA, VFBGA  
suitable  
suitable  
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,  
HTSSOP, HVQFN, HVSON, SMS  
not suitable(4)  
PLCC(5), SO, SOJ  
LQFP, QFP, TQFP  
SSOP, TSSOP, VSO, VSSOP  
PMFP(8)  
suitable  
suitable  
not recommended(5)(6) suitable  
not recommended(7)  
suitable  
not suitable  
not suitable  
Notes  
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy  
from your Philips Semiconductors sales office.  
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum  
temperature (with respect to time) and body size of the package, there is a risk that internal or external package  
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the  
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.  
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account  
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature  
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature  
must be kept as low as possible.  
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder  
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,  
the solder might be deposited on the heatsink surface.  
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.  
The package footprint must incorporate solder thieves downstream and at the side corners.  
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not  
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.  
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than  
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.  
8. Hot bar or manual soldering is suitable for PMFP packages.  
2003 Nov 07  
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Philips Semiconductors  
Product specification  
SDH/SONET, Fibre Channel and Gigabit  
Ethernet multi-rate fibre optic transmitter  
TZA3057HW  
DATA SHEET STATUS  
DATA SHEET  
STATUS(1)  
PRODUCT  
STATUS(2)(3)  
LEVEL  
DEFINITION  
I
Objective data  
Development This data sheet contains data from the objective specification for product  
development. Philips Semiconductors reserves the right to change the  
specification in any manner without notice.  
II  
Preliminary data Qualification  
This data sheet contains data from the preliminary specification.  
Supplementary data will be published at a later date. Philips  
Semiconductors reserves the right to change the specification without  
notice, in order to improve the design and supply the best possible  
product.  
III  
Product data  
Production  
This data sheet contains data from the product specification. Philips  
Semiconductors reserves the right to make changes at any time in order  
to improve the design, manufacturing and supply. Relevant changes will  
be communicated via a Customer Product/Process Change Notification  
(CPCN).  
Notes  
1. Please consult the most recently issued data sheet before initiating or completing a design.  
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was  
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.  
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.  
DEFINITIONS  
DISCLAIMERS  
Short-form specification  
The data in a short-form  
Life support applications  
These products are not  
specification is extracted from a full data sheet with the  
same type number and title. For detailed information see  
the relevant data sheet or data handbook.  
designed for use in life support appliances, devices, or  
systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips  
Semiconductors customers using or selling these products  
for use in such applications do so at their own risk and  
agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in  
accordance with the Absolute Maximum Rating System  
(IEC 60134). Stress above one or more of the limiting  
values may cause permanent damage to the device.  
These are stress ratings only and operation of the device  
at these or at any other conditions above those given in the  
Characteristics sections of the specification is not implied.  
Exposure to limiting values for extended periods may  
affect device reliability.  
Right to make changes  
Philips Semiconductors  
reserves the right to make changes in the products -  
including circuits, standard cells, and/or software -  
described or contained herein in order to improve design  
and/or performance. When the product is in full production  
(status ‘Production’), relevant changes will be  
Application information  
Applications that are  
communicated via a Customer Product/Process Change  
Notification (CPCN). Philips Semiconductors assumes no  
responsibility or liability for the use of any of these  
products, conveys no licence or title under any patent,  
copyright, or mask work right to these products, and  
makes no representations or warranties that these  
products are free from patent, copyright, or mask work  
right infringement, unless otherwise specified.  
described herein for any of these products are for  
illustrative purposes only. Philips Semiconductors make  
no representation or warranty that such applications will be  
suitable for the specified use without further testing or  
modification.  
2003 Nov 07  
22  
Philips Semiconductors – a worldwide company  
Contact information  
For additional information please visit http://www.semiconductors.philips.com.  
Fax: +31 40 27 24825  
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.  
© Koninklijke Philips Electronics N.V. 2003  
SCA75  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed  
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license  
under patent- or other industrial or intellectual property rights.  
Printed in The Netherlands  
403510/02/pp23  
Date of release: 2003 Nov 07  
Document order number: 9397 750 11711  
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