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5V5218PGGI8

型号：

5V5218PGGI8

品牌：

IDT[ INTEGRATED DEVICE TECHNOLOGY ]

页数：

24 页

PDF大小：

434 K

下载PDF手册
Dual Channel Type-1/Type-2 M-LVDS to  
LVTTL/LVPECL/LVDS Transceiver  
IDT5V5218  
Version -  
May 18, 2006  
6024 Silver Creek Valley Road, San Jose, CA 95138  
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775  
Printed in U.S.A.  
© 2006 Integrated Device Technology, Inc.  
DISCLAIMER  
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance  
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The  
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is  
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.  
LIFE SUPPORT POLICY  
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to  
such intended use is executed between the manufacturer and an officer of IDT.  
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,  
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.  
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device  
or system, or to affect its safety or effectiveness.  
Table of Contents  
TABLE OF CONTENTS ........................................................................................................................................................... 3  
LIST OF TABLES .................................................................................................................................................................... 4  
LIST OF FIGURES ................................................................................................................................................................... 5  
FEATURES.............................................................................................................................................................................. 6  
APPLICATIONS....................................................................................................................................................................... 6  
DESCRIPTION......................................................................................................................................................................... 6  
FUNCTIONAL BLOCK DIAGRAM.......................................................................................................................................... 7  
1
2
3
PIN ASSIGNMENT .......................................................................................................................................................... 8  
PIN DESCRIPTION ......................................................................................................................................................... 9  
ELECTRICAL SPECIFICATION ................................................................................................................................... 11  
3.1  
3.2  
ABSOLUTE MAXIMUM RATING AND RECOMMENDED OPERATION CONDITIONS ................................. 11  
LVTTL/LVDS/LVPECL DRIVER/RECEIVER CHARACTERISTICS ................................................................ 12  
3.2.1 M-LVDS to LVTTL................................................................................................................................ 12  
3.2.2 M-LVDS to LVDS ................................................................................................................................. 13  
3.2.3 M-LVDS to LVPECL............................................................................................................................. 16  
M-LVDS DRIVER TYPE-1/TYPE-2 RECEIVER CHARACTERISTICS ............................................................ 17  
3.3  
ORDERING INFORMATION.................................................................................................................................................. 24  
Table of Contents  
3
May 18, 2006  
List of Tables  
Table-1  
Table-2  
Table-3  
Table-4  
Table-5  
Table-6  
Table-7  
Table-8  
Table-9  
Table-10  
Table-11  
Table-12  
Table-13  
Table-14  
Table-15  
Table-16  
Table-17  
Pin Description............................................................................................................................................... 9  
Absolute Maximum Rating........................................................................................................................... 11  
Recommended Operation Conditions.......................................................................................................... 11  
LVTTL DC Parameters ................................................................................................................................ 12  
LVTTL AC Parameters................................................................................................................................. 12  
LVDS DC Parameters.................................................................................................................................. 13  
LVDS AC Parameters.................................................................................................................................. 15  
Differential LVPECL DC Parameters ........................................................................................................... 16  
Differential LVPECL AC Parameters ........................................................................................................... 16  
M-LVDS Type-1 Receiver Input Threshold Test Voltages........................................................................... 17  
M-LVDS Type-2 Receiver Input Threshold Test Voltages........................................................................... 17  
M-LVDS DC Parameters.............................................................................................................................. 18  
M-LVDS Input Current Parameters.............................................................................................................. 20  
M-LVDS AC Parameters.............................................................................................................................. 21  
M-LVDS Type-1/Type-2 Receiver AC Parameters ...................................................................................... 22  
M-LVDS Receiver output DC Parameters ................................................................................................... 23  
M-LVDS Driver AC Parameter..................................................................................................................... 23  
List of Tables  
4
May 18, 2006  
List of Figures  
Figure-1  
Figure-2  
Figure-3  
Figure-4  
Figure-5  
Figure-6  
Figure-7  
Figure-8  
Figure-9  
Figure-10  
Figure-11  
Figure-12  
Figure-13  
Figure-14  
Figure-15  
Figure-16  
Functional Block Diagram .............................................................................................................................. 7  
IDT5V5218 TSSOP24 Package Pin Assignment ........................................................................................... 8  
LVTTL Output Test Circuit and Waveforms ................................................................................................. 12  
LVDS Receiver Input Common-mode Range Test Circuit ........................................................................... 13  
LVDS Driver Output Voltage Test Circuit ..................................................................................................... 14  
LVDS Driver Shorted to Ground .................................................................................................................. 14  
LVDS Driver Shorted Together .................................................................................................................... 14  
LVDS Output Test Circuit ............................................................................................................................. 15  
LVPECL Driver Output Test Circuit and Waveforms ................................................................................... 16  
M-LVDS Driver Output Voltage Test Circuit ................................................................................................. 18  
M-LVDS Driver Short-Circuit Test Circuit ..................................................................................................... 18  
M-LVDS Type-1/Type-2 Receiver Input Common-mode Range Test Circuit .............................................. 19  
Various Input Currents Test Circuit .............................................................................................................. 20  
Differential Skew .......................................................................................................................................... 21  
M-LVDS Output Voltage Test Circuit ........................................................................................................... 21  
Timing and Voltage Definitions for the Output Signal .................................................................................. 23  
List of Figures  
5
May 18, 2006  
Dual Channel Type-1/Type-2 M-  
LVDS to LVTTL/LVPECL/LVDS  
IDT5V5218  
‹
Other Features  
FEATURES  
–
–
–
Low power consumption < 220 mW  
Hot swappable  
24-pin TSSOP package  
‹
Main Features  
–
–
–
Two independent channels  
Type-2 M-LVDS receiver supports 100 mV offset threshold  
Up to 166 MHz selectable input/output signals: LVTTL/  
LVPECL/LVDS  
APPLICATIONS  
–
–
–
M-LVDS interface allows common-mode voltage: -1 V to 3.4 V  
Power up and power down glitch free  
M-LVDS interface pins in high impedance state when the  
device is powered down or VDD < 1.5 V  
–
–
–
–
Backplane transmission  
Telecommunication system  
Data communications  
ATCA clock distribution  
–
Capable of driving bus load from 30 Ω to 55 Ω  
DESCRIPTION  
The IDT5V5218 is a dual-channel transceiver which can interchange  
data across multipoint data bus structures.  
between LVTTL/LVPECL/LVDS signals and M-LVDS signals. The  
drivers and the receivers can be enabled or disabled by external pins.  
The M-LVDS driver is capable of driving bus load from 30 Ω to 55 Ω.  
The M-LVDS interface allows common-mode voltage range of -1 V to  
3.4 V.  
In the device, the two channels operate independently. Each channel  
has selectable LVTTL/LVPECL/LVDS drivers and receivers, a selectable  
Type-1/Type-2 M-LVDS receiver and M-LVDS driver. It translates  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
6
May 18, 2006  
DSC-6966/-  
2006 Integrated Device Technology, Inc.  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
FUNCTIONAL BLOCK DIAGRAM  
RE1_EN  
OUT1_A  
OUT1_B  
LVTTL/LVPECL/  
LVDS Interface 1  
IN1_A  
IN1_B  
M1_A  
M-LVDS Interface 1  
M1_B  
DR1_EN  
RE2_EN  
OUT2_A  
OUT2_B  
LVTTL/LVPECL/  
LVDS Interface 2  
M2_A  
IN2_A  
IN2_B  
M-LVDS Interface 2  
M2_B  
DR2_EN  
DIFF_SEL  
I/O Config  
TYPE_SEL  
Figure-1 Functional Block Diagram  
Functional Block Diagram  
7
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
1
PIN ASSIGNMENT  
DR2_EN  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
RE2_EN  
OUT2_B  
OUT2_A  
DIFF_SEL  
TYPE_SEL  
VDD1  
IN2_A  
IN2_B  
OUT1_A  
OUT1_B  
RE1_EN  
DR1_EN  
IN1_A  
IN1_B  
NC  
2
3
4
5
6
IDT5V5218  
7
M1_B  
8
M1_A  
9
GND1  
10  
11  
12  
VDD2  
NC  
M2_B  
GND2  
M2_A  
Figure-2 IDT5V5218 TSSOP24 Package Pin Assignment  
Pin Assignment  
8
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
2
PIN DESCRIPTION  
Table-1 Pin Description  
Name  
Pin No.  
I/O  
Type  
Description  
Global Signal  
I
DR1_EN: M-LVDS Driver 1 Enable  
This pin controls the M-LVDS driver for channel 1: high for enable and low for disable.  
DR1_EN  
RE1_EN  
DR2_EN  
RE2_EN  
7
6
LVTTL  
LVTTL  
LVTTL  
LVTTL  
Pull-down  
RE1_EN: Type-1/Type-2 M-LVDS Receiver 1 and LVTTL/LVPECL/LVDS Drivers 1 Enable  
This pin controls the Type-1/Type-2 M-LVDS receiver and LVTTL/LVPECL/LVDS drivers for  
channel 1: high for disable and low for enable. Note that the LVTTL driver is in high impedance  
state when disabled.  
I
Pull-up  
I
DR2_EN: M-LVDS Driver 2 Enable  
This pin controls the M-LVDS driver for channel 2: high for enable and low for disable.  
1
Pull-down  
RE2_EN: Type-1/Type-2 M-LVDS Receiver 2 and LVTTL/LVPECL/LVDS Drivers 2 Enable  
This pin controls the Type-1/Type-2 M-LVDS receiver and LVTTL/LVPECL/LVDS drivers for  
channel 2: high for disable and low for enable. Note that the LVTTL driver is in high impedance  
state when disabled.  
I
24  
Pull-up  
TYPE_SEL: Type-1/Type-2 M-LVDS Receiver Selection  
This pin globally controls the Type-1/Type-2 M-LVDS receiver selection: high for Type-2 and  
low for Type-1.  
I
TYPE_SEL  
DIFF_SEL  
20  
21  
LVTTL  
LVTTL  
Pull-down  
DIFF_SEL: Type Selection for LVTTL/LVPECL/LVDS Interface Input/Output 1 and 2  
This pin globally determines the type of input/output 1 and 2 of the LVTTL/LVPECL/LVDS  
interface: high for LVDS, floating for LVTTL and low for LVPECL.  
I
Pull to VDD/2  
LVTTL/LVPECL/LVDS Interface  
IN1_A/IN1_B: Positive/Negative LVPECL/LVDS Input 1  
An up to 166 MHz differential signal is input on this pair of pins. The input signal can be  
LVPECL or LVDS, as selected by the DIFF_SEL pin.  
IN1_A  
IN1_B  
8
9
LVTTL/LVPECL/LVDS  
LVPECL/LVDS  
I
I
IN1_A: LVTTL Input 1  
An up to 166 MHz LVTTL signal is input on this pin, as selected by the DIFF_SEL pin. In this  
case, the IN1_B pin will be in high impedance state.  
IN2_A/IN2_B: Positive/Negative LVPECL/LVDS Input 2  
An up to 166 MHz differential signal is input on this pair of pins. The input signal can be  
LVPECL or LVDS, as selected by the DIFF_SEL pin.  
IN2_A  
IN2_B  
2
3
LVTTL/LVPECL/LVDS  
LVPECL/LVDS  
IN2_A: LVTTL Input 2  
An up to 166 MHz LVTTL signal is input on this pin, as selected by the DIFF_SEL pin. In this  
case, the IN2_B pin will be in high impedance state.  
OUT1_A/OUT1_B: Positive/Negative LVPECL/LVDS Output 1  
This pair of pins output an up to 166 MHz differential signal. The output signal can be LVPECL  
or LVDS, as selected by the DIFF_SEL pin.  
OUT1_A  
OUT1_B  
4
5
LVTTL/LVPECL/LVDS  
LVPECL/LVDS  
O
OUT1_A: LVTTL Output 1  
This pin outputs an up to 166 MHz LVTTL signal, as selected by the DIFF_SEL pin. In this  
case, the OUT1_B pin will be in high impedance state.  
Pin Description  
9
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
Table-1 Pin Description (Continued)  
Name  
Pin No.  
I/O  
Type  
Description  
OUT2_A/OUT2_B: Positive/Negative LVPECL/LVDS Output 2  
This pair of pins output an up to 166 MHz differential signal. The output signal can be LVPECL  
or LVDS, as selected by the DIFF_SEL pin.  
OUT2_A  
OUT2_B  
22  
23  
LVTTL/LVPECL/LVDS  
LVPECL/LVDS  
O
OUT2_A: LVTTL Output 2  
This pin outputs an up to 166 MHz LVTTL signal, as selected by the DIFF_SEL pin. In this  
case, the OUT2_B pin will be in high impedance state.  
M-LVDS Interface  
M1_A  
M1_B  
17  
18  
M1_A/M1_B: Positive/Negative M-LVDS Data Bus Interface 1  
This pair of pins are connected to the M-LVDS data bus.  
I/O  
I/O  
M-LVDS  
M-LVDS  
M2_A  
M2_B  
13  
14  
M2_A/M2_B: Positive/Negative M-LVDS Data Bus Interface 2  
This pair of pins are connected to the M-LVDS data bus.  
Power Supply and Ground  
3.3 V Power Supply for Channel 1  
3.3 V Power Supply for Channel 2  
Ground for Channel 1  
VDD1  
VDD2  
GND1  
GND2  
19  
15  
16  
12  
Power  
Power  
-
-
-
-
Ground  
Ground  
Ground for Channel 2  
Others  
NC  
10, 11  
-
-
NC: No Connection  
Pin Description  
10  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
3
ELECTRICAL SPECIFICATION  
3.1 ABSOLUTE MAXIMUM RATING AND RECOMMENDED OPERATION CONDITIONS  
Table-2 Absolute Maximum Rating  
Symbol  
Parameter  
Range  
VDD  
VIN  
Supply Voltage  
-0.5 V to 4.1 V  
-0.5 V to 4.1 V  
-1.8 V to 4 V  
-0.3 V to 4 V  
-1.8 V to 4 V  
±8 kV  
Input Voltage  
Output Voltage  
REn_EN(1), DRn_EN, INn_A, INn_B  
Mn_A, Mn_B  
OUTn_A, OUTn_B  
Mn_A, Mn_B  
VOUT  
Electrostatic Discharge  
Human Body Model Mn_A, Mn_B  
All pins  
±2 kV  
TJ  
Junction Temperature  
Storage Temperature  
150°C  
TS  
-65°C to 165°C  
1. n = 1, 2  
Table-3 Recommended Operation Conditions  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
VDD  
Power Supply  
3.0  
2
3.3  
3.6  
3.0  
0.8  
3.8  
3.0  
85  
V
V
VIH  
VIL  
High Level Input Voltage  
Low Level Input Voltage  
0
V
Voltage at any Bus Terminal  
Magnitude of Differential Input Voltage  
Ambient Operating Temperature  
-1.4  
0.05  
-40  
V
V
TA  
°C  
Electrical Specification  
11  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
3.2 LVTTL/LVDS/LVPECL DRIVER/RECEIVER CHARACTERISTICS  
3.2.1 M-LVDS TO LVTTL  
Table-4 LVTTL DC Parameters  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
VIHL  
VILL  
IILL  
Input High Level  
Input Low Level  
2.0  
-0.3  
-1.0  
2.4  
VDD + 0.3  
0.8  
V
V
Input Leakage Current  
Output High Voltage  
Output Low Voltage  
1.0  
µA  
V
VOHL  
VOLL  
Output Current = 17 mA, VDD = 3 V  
Output Current = 12 mA, VDD = 3 V  
0.4  
V
Table-5 LVTTL AC Parameters  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
tr  
tf  
Rise Time  
Fall Time  
Frequency  
Cload = 15 pF, 10% - 90%  
Cload = 15 pF, 10% - 90%  
1.2  
1.2  
ns  
ns  
fML  
166  
MHz  
OUTn  
VOUT  
15 pF  
VA  
1.2 V  
VB  
1.0 V  
VID  
0.2 V  
0 V  
-0.2 V  
tpHL  
tpLH  
VO  
VOH  
VOL  
90%  
10%  
tf  
tr  
Figure-3 LVTTL Output Test Circuit and Waveforms  
Electrical Specification  
12  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
3.2.2 M-LVDS TO LVDS  
Table-6 LVDS DC Parameters  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
VCM  
VDIFF  
VIDTH  
IIN  
Input Common-mode Voltage Range  
Input Peak Differential Voltage  
Input Differential Threshold  
Input Leakage Current  
0
1200  
2400  
900  
100  
20  
mV  
mV  
mV  
µA  
100  
-100  
VOH  
VOL  
Output Voltage High  
Rload = 100 Ω ± 1%  
Rload = 100 Ω ± 1%  
Rload = 100 Ω ± 1%  
Rload = 100 Ω ± 1%  
1350  
925  
250  
1100  
80  
1475  
1100  
450  
1300  
120  
25  
mV  
mV  
mV  
mV  
Ohm  
mV  
mV  
mA  
mA  
Output Voltage Low  
VOD  
VOS  
Differential Output Voltage  
Output Offset Voltage  
R0  
Differential Output Impedance  
Change in VOD between Logic 0 and Logic 1  
Change in VOS between Logic 0 and Logic 1  
Output Current  
V
CM = 1.0 V or 1.4 V  
100  
∆VOD  
∆VOS  
Rload = 100 Ω ± 1%  
Rload = 100 Ω ± 1%  
Driver shorted to GND  
Driver shorted together  
25  
I
SAISB  
24  
ISAB  
Output Current  
12  
10 kΩ  
INn_A  
Mn_A  
VOUT  
LVTTL/LVPECL/  
LVDS Interface  
M-LVDS Interface  
INn_B  
1 µF  
10 kΩ  
Mn_B  
+
-
VTEST  
0 V to 2.4 V  
1 µF  
0~166 MHz  
Figure-4 LVDS Receiver Input Common-mode Range Test Circuit  
Electrical Specification  
13  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
50 W  
OUTn_A  
OUTn_B  
VOD  
VOS  
50 W  
VA  
VB  
1.2 V  
1.0 V  
VID  
0.2 V  
0 V  
-0.2 V  
tpHL  
tpLH  
VO  
VOH  
VOL  
80%  
20%  
tf  
tr  
Figure-5 LVDS Driver Output Voltage Test Circuit  
OUTn_A  
High or Low Steady  
State Logic Input  
+
-
VTEST  
OUTn_B  
-1 V to 3.4 V  
Figure-6 LVDS Driver Shorted to Ground  
OUTn_A  
High or Low Steady  
State Logic Input  
OUTn_B  
Figure-7 LVDS Driver Shorted Together  
Electrical Specification  
14  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
Table-7 LVDS AC Parameters  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
tr  
tf  
Rise Time  
Fall Time  
20% - 80%  
20% - 80%  
150  
150  
-50  
350  
350  
50  
ps  
ps  
tTSP  
fMM  
Differential Skew  
Frequency  
ps  
166  
MHz  
OUTn_A  
3.74 kΩ  
3.74 kΩ  
High or Low Steady  
State Logic Input  
VT  
100 Ω  
+
VTEST  
0 V to 2.4 V  
OUTn_B  
-
Figure-8 LVDS Output Test Circuit  
Electrical Specification  
15  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
3.2.3 M-LVDS TO LVPECL  
Table-8 Differential LVPECL DC Parameters  
Symbol  
Parameter  
Min  
Typ  
Max  
Unit  
VIL  
VIH  
VID  
IIH  
Input Low Voltage, Differential Inputs  
Input High Voltage, Differential Inputs  
Input Differential Voltage  
VDD-2.5  
VDD-2.4  
0.1  
VDD-0.5  
VDD-0.4  
1.4  
V
V
V
Input High Current, VID = 1.4 V  
Input Low Current, VID = 1.4 V  
Output Voltage Low  
-10  
10  
µA  
µA  
V
IIL  
-10  
10  
VOL  
VOH  
VOS  
VDD-2.1  
VDD-1.25  
580  
VDD-1.6  
VDD-0.88  
950  
Output Voltage High  
V
Output Differential Voltage  
mV  
OUTn_A  
OUTn_B  
50 Ω  
50 Ω  
VOS  
VDD - 2 V  
VA  
VB  
1.2 V  
1.0 V  
VID  
0.2 V  
0 V  
-0.2 V  
tpHL  
tpLH  
VO  
VOH  
VOL  
80%  
20%  
tf  
tr  
Figure-9 LVPECL Driver Output Test Circuit and Waveforms  
Table-9 Differential LVPECL AC Parameters  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
tr  
tf  
Rise Time  
Fall Time  
20% - 80%  
20% - 80%  
150  
150  
-50  
350  
350  
50  
ps  
ps  
tTSP  
fMM  
Differential Skew  
Frequency  
ps  
166  
MHz  
Electrical Specification  
16  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
3.3 M-LVDS DRIVER TYPE-1/TYPE-2 RECEIVER CHARACTERISTICS  
Table-10 M-LVDS Type-1 Receiver Input Threshold Test Voltages  
Applied Voltages  
Resulting Differential Input Voltage  
Resulting Common-mode Input Voltage  
Receiver Output(1)  
VA  
VB  
2.400  
0.000  
3.425  
3.375  
-0.975  
-1.025  
0.000  
2.400  
3.375  
3.425  
-1.025  
-0.975  
2.400  
-2.400  
0.050  
-0.050  
0.050  
-0.050  
1.200  
1.200  
3.4  
High  
Low  
High  
Low  
High  
Low  
3.4  
-1  
-1  
1. The receiver is enabled ( The RE1_EN or RE2_EN pin is pulled low).  
Table-11 M-LVDS Type-2 Receiver Input Threshold Test Voltages  
Applied Voltages  
Resulting Differential Input Voltage  
Resulting Common-mode Input Voltage  
Receiver Output(1)  
VA  
VB  
2.400  
0.000  
3.475  
3.425  
-0.925  
-0.975  
0.000  
2.400  
3.325  
3.375  
-1.075  
-1.025  
2.400  
-2.400  
0.150  
0.050  
0.150  
0.050  
1.200  
1.200  
3.4  
High  
Low  
High  
Low  
High  
Low  
3.4  
-1  
-1  
1. The receiver is enabled (The RE1_EN or RE2_EN pin is pulled low).  
Electrical Specification  
17  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
Table-12 M-LVDS DC Parameters  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
VODM  
Differential Output Voltage  
480  
-50  
650  
50  
mV  
mV  
∆VODM  
Change in VODM for Complimentary Output States,  
∆VODM = |VODM1 - VODM0  
|
VOSM  
∆VOSM  
VOSM(p-p)  
IOM  
Offset Voltage  
0.8  
-50  
1.2  
50  
V
Change in VOSM for Complimentary Output States  
Peak-to-peak Common-mode Output Voltage  
Output Short Circuit Current  
mV  
mV  
mA  
µA  
mV  
150  
20  
IIZM  
High Impedance Input Current  
-10  
10  
VTHM  
Differential Input High Threshold  
Type-1  
Type-2  
50  
150  
VTLM  
Differential Input Low Threshold  
Type-1  
Type-2  
-50  
+50  
mV  
VCMM  
IINM  
Input Common-mode Range  
Input Current  
VINA - VINB = 200 mV  
-1  
3.4  
20  
V
Input Voltage = 0 V to 2.4 V  
-20  
µA  
24.9 Ω  
24.9 Ω  
∆VOSM  
Mn_A  
Mn_B  
VOSM(p-p)  
VODM  
VOSM  
VOSM  
VAB  
0 V  
VODM0  
VODM1  
Figure-10 M-LVDS Driver Output Voltage Test Circuit  
Mn_A  
High or Low Steady  
State Logic Input  
+
-
VTEST  
- 1 V to 3.4 V  
Mn_B  
Figure-11 M-LVDS Driver Short-Circuit Test Circuit  
Electrical Specification  
18  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
10 kΩ  
10 kΩ  
Mn_A  
M-LVDS Interface  
Mn_B  
OUTn_A  
LVTTL/LVPECL/  
LVDS Interface  
VOUT  
OUTn_B  
+
VTEST  
-
-1 V to 3.4 V  
1 µF  
1 µF  
0 ~ 166 MHz  
Figure-12 M-LVDS Type-1/Type-2 Receiver Input Common-mode Range Test Circuit  
Electrical Specification  
19  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
Table-13 M-LVDS Input Current Parameters  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Unit  
IA  
Receiver or Transceiver with Driver Disabled Input Current  
VA = 3.8 V, VB = 1.2 V  
VA = 0 V or 2.4 V, VB = 1.2 V  
0
32  
20  
0
µA  
-20  
-32  
0
VA = - 1.4 V, VB = 1.2 V  
IB  
Receiver or Transceiver with Driver Disabled Input Current  
VB = 3.8 V, VA = 1.2 V  
32  
20  
0
µA  
VB = 0 V or 2.4 V, VA = 1.2 V  
-20  
-32  
-4  
VB = -1.4 V, VA = 1.2 V  
IAB  
Receiver or Transceiver with Driver Differential Current (IA - IB)  
Receiver or Transceiver Power-off Input Current  
VA = VB, -1.4 V < VA < 3.8 V  
4
µA  
µA  
IA(OFF)  
VA = 3.8 V, VB = 1.2 V, 0 V < VDD < 1.5 V  
VA = 0 or 2.4 V, VB = 1.2 V, 0 V < VDD < 1.5 V  
VA = -1.4 V, VB = 1.2 V, 0 V < VDD < 1.5 V  
VB = 3.8 V, VA = 1.2 V, 0 V < VDD < 1.5 V  
VB = 0 or 2.4 V, VA = 1.2 V, 0 V < VDD < 1.5 V  
VB = -1.4 V, VA = 1.2 V, 0 V < VDD < 1.5 V  
0
32  
20  
0
-20  
-32  
0
IB(OFF)  
Receiver or Transceiver Power-off Input Current  
32  
20  
0
µA  
-20  
-32  
-4  
IAB(OFF) Receiver or Transceiver Power-off Differential Input Current (IA - IB) VA = VB, 0 V < VDD< 1.5 V, -1.4 V < VA < 3.8 V  
4
µA  
pF  
CAB  
Transceiver with driver disabled differential input capacitance  
VAB = 0.4 sin (30E6πt) V  
4
Mn_A  
Mn_B  
V
A
V
B
Figure-13 Various Input Currents Test Circuit  
Electrical Specification  
20  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
Table-14 M-LVDS AC Parameters  
Symbol  
Parameter  
Test Conditions  
Min.  
Typ  
Max.  
Unit  
tr  
tf  
Rise Time  
Fall Time  
10% - 90%  
10% - 90%  
0.8  
0.8  
1.5  
1.5  
ns  
ns  
tTSL  
fML  
Differential Skew, tTSL = {tTSL1, tTSL2  
Frequency  
}
-100  
100  
166  
ps  
MHz  
VA  
tTSL1  
tTSL2  
VB  
Figure-14 Differential Skew  
3.32 kΩ  
Mn_A  
VODM  
50 Ω  
+
VTEST  
-1 V to 3.4 V  
-
Mn_B  
3.32 kΩ  
Figure-15 M-LVDS Output Voltage Test Circuit  
Electrical Specification  
21  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
Table-15 M-LVDS Type-1/Type-2 Receiver AC Parameters  
Output mode  
Symbol  
Parameter  
Test Condition  
Min Typ Max Unit  
LVTTL  
tpLH  
tpHL  
Type-1  
Type-2  
Delay, Low to High Level  
Delay, High to Low Level  
Pulse Skew, tsk = |tpLH - tpHL  
Input clock: freq = 50 MHz, Impedance = 150 Ω,  
Voltage = -200 mV - 200 mV. See Figure-3  
2.5 5.5  
2.5 5.5  
6.5  
6.5  
ns  
ns  
ps  
ps  
ns  
ns  
ps  
ps  
ns  
ns  
ps  
ps  
ps  
ps  
ps  
ps  
ns  
ns  
ps  
ps  
ps  
ps  
ps  
ps  
tsk  
|
100 300  
300 500  
2.4  
Tr (10% - 90%)  
Tf (10% - 90%)  
Tjit(per)  
Rise Time  
Fall Time  
1
1
2.4  
Period jitter, rms(1 standard deviation)  
Output to Output Skew  
4
7
200  
5.5  
5.5  
LVDS  
tpLH  
tpHL  
Delay, Low to High Level  
Input clock: freq = 50 MHz, Impedance = 150 Ω,  
Voltage = -200 mV - 200 mV. See Figure-5  
2.5 4.0  
2.5 4.0  
Delay, High to Low Level  
tsk  
Type-1  
Type-2  
Pulse Skew, tsk = |tpLH - tpHL  
|
150 300  
250 500  
Tr (20% - 80%)  
Tf (20% - 80%)  
Tjit(per)  
Rise Time  
Fall Time  
150 200 350  
150 200 350  
Period jitter, rms(1 standard deviation)  
Output to Output Skew  
4
7
200  
5.5  
5.5  
LVPECL  
tpLH  
tpHL  
Delay, Low to High Level  
Input clock: freq = 50 MHz, Impedance = 150 Ω,  
Voltage = -200 mV - 200 mV. See Figure-9  
2.5  
2.5  
4
4
Delay, High to Low Level  
tsk  
Type-1  
Type-2  
Pulse Skew, tsk = |tpLH - tpHL  
|
150 300  
200 500  
Tr (20% - 80%)  
Tf (20% - 80%)  
Tjit(per)  
Rise Time  
Fall Time  
150 250 350  
150 250 350  
Period jitter, rms(1 standard deviation)  
Output to Output Skew  
4
7
200  
Electrical Specification  
22  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
Table-16 M-LVDS Receiver output DC Parameters  
Output mode  
Symbol  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
LVPECL  
LVDS  
VOD  
VOS  
VOD  
Differential Output Voltage  
Output Offset Voltage  
Differential Output Voltage  
Output Current  
580  
1100  
250  
950  
1300  
450  
28  
mV  
mV  
mV  
mA  
mV  
1200  
350  
I
SA, ISB  
VODM  
Differential Output Voltage  
480  
650  
Table-17 M-LVDS Driver AC Parameter  
Symbol  
Parameter  
Test Condition  
Min  
Typ  
Max  
Unit  
tpLH  
tpHL  
Delay, Low to High Level  
Delay, High to Low Level  
Pulse Skew, tsk = |tpLH - tpHL|  
Input clock: freq = 15 MHz, Tr = Tf =  
1.2 ns, Impedance = 300 Ω,  
Voltage = 0 V - 3.3 V. See Figure-10  
2.5  
2.5  
3.7  
3.7  
40  
5.5  
5.5  
100  
400  
1.5  
1.5  
3
ns  
ns  
ps  
ps  
ns  
ns  
ps  
ps  
Tsk  
LVTTL input  
LVDS/LVPECL input  
250  
1.1  
1.1  
2
Tr (10% - 90%)  
Rise Time  
Fall Time  
0.7  
0.7  
Tf (10% - 90%)  
Tjit(per)  
Period jitter, rms (1 standard deviation)  
Output to Output Skew  
100  
Input  
tpLH  
tpHL  
Vs  
0.8Vs/0.9Vs  
Output  
0.2Vs/0.1Vs  
tf  
0 Vs  
tr  
Figure-16 Timing and Voltage Definitions for the Output Signal  
Electrical Specification  
23  
May 18, 2006  
IDT5V5218  
Dual Channel Type-1/Type-2 M-LVDS to LVTTL/LVPECL/LVDS Transceiver  
ORDERING INFORMATION  
XXXXXXX  
Device Type  
XX  
X
IDT  
Process/  
Temperature  
Range  
I
Industrial (-40 °C to +85 °C)  
Green Thin Shrink Small Outline Package (TSSOP, PGG24)  
PGG  
Dual Channel Type-1/Type-2 M-LVDS to  
LVTTL/LVPECL/LVDS Transceiver  
5V5218  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
for Tech Support:  
408-360-1552  
email:TELECOMhelp@idt.com  
1-800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  
24  
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