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TPS70445, TPS70448

TPS70451, TPS70458

TPS70402

www.ti.com

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS

Check for Samples: TPS70445, TPS70448, TPS70451, TPS70458, TPS70402

1

FEATURES

DESCRIPTION

23

•

Dual Output Voltages for Split-Supply

The TPS704xx family of devices consists of

dual-output, low-dropout voltage regulators with

integrated SVS (RESET, POR, or power on reset)

and power good (PG) functions. These devices are

capable of supplying 1 A and 2 A by regulator 1 and

regulator 2 respectively. Quiescent current is typically

185 mA at full load. Differentiated features, such as

accuracy, fast transient response, SVS supervisory

circuit (power on reset), manual reset input, and

independent enable functions provide a complete

system solution.

Applications

•

Independent Enable Functions (See Part

Number TPS703xx for Sequenced Outputs)

•

Output Current Range of 1 A on Regulator 1

and 2 A on Regulator 2

•

Fast Transient Response

Voltage Options: 3.3-V/2.5-V, 3.3-V/1.8-V,

3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable

Outputs

PWP PACKAGE

(TOP VIEW)

•

Open Drain Power-On Reset with 120-ms Delay

Open Drain Power Good for Regulator 1 and

Regulator 2

GND/HEATSINK

1

24

23

22

21

20

19

18

17

16

15

14

13

V_IN1

2

V_OUT1

V_SENSE1/FB1

NC

•

Ultralow 185mA (typ) Quiescent Current

2mA Input Current During Standby

Low Noise: 78mV_RMSWithout Bypass Capacitor

Quick Output Capacitor Discharge Feature

One Manual Reset Input

V_IN1

3

4

NC

MR

5

EN1

EN2

6

PG1

7

PG2

RESET

8

NC

2% Accuracy Over Load and Temperature

Undervoltage Lockout (UVLO) Feature

24-Pin PowerPAD™ TSSOP Package

Thermal Shutdown Protection

9

GND

V_SENSE2/FB2

V_OUT2

V_IN2

10

11

12

V_IN2

V_OUT2

GND/HEATSINK

NC = No internal connection

TPS70451 PWP

V

I/O

3.3 V

OUT1

5 V

V

IN1

22 mF

0.22 mF

V

SENSE1

250 kW

PG1

MR

>2 V

V

IN2

<0.7 V

0.22 mF

EN1

RESET

PG2

>2 V

PG2

EN1

EN2

<0.7 V

EN2

V

SENSE2

1.8 V

Core

V

OUT2

47 mF

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

PowerPAD is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS70445, TPS70448

TPS70451, TPS70458

TPS70402

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

www.ti.com

The TPS704xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have

extremely low noise output performance without using any added filter bypass capacitors and are designed to

have a fast transient response and be stable with 47-mF low ESR capacitors.

These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.

Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the

designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV on

regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a

voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 250 mA

over the full range of output current and full range of temperature). This LDO family also features a sleep mode;

applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high

signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2

mA at T_J= +25°C.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator

is turned off (disabled).

The PG1 pin reports the voltage condition at V_OUT1. The PG1 pin can be used to implement a SVS (RESET,

POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at

V_OUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.

The TPS704xx features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output

and requires a pull-up resistor for normal operation. When pulled up, RESET goes into a high impedance state

(that is, logic high) after a 120-ms delay when both of the following conditions are met. First, V_IN1must be above

the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor

V_OUT1, the PG1 output pin can be connected to MR. To monitor V_OUT2, the PG2 output pin can be connected to

MR. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can be left

floating.

Internal bias voltages are powered by V_IN1and require 2.7 V for full functionality. Each regulator input has an

undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.

2

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SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

VOLTAGE (V)⁽²⁾

PACKAGE-

LEAD

SPECIFIED

TEMPERATURE

RANGE (T_J)

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

V_OUT1

V_OUT2

(DESIGNATOR)

TPS70402PWP

TPS70402PWPR

TPS70445PWP

TPS70445PWPR

TPS70448PWP

TPS70448PWPR

TPS70451PWP

TPS70451PWPR

TPS70458PWP

TPS70458PWPR

Tube, 60

Tape and Reel, 2000

Tube, 60

TPS70402

Adjustable

Adjustable HTSSOP-24 (PWP)

–40°C to +125°C

TPS70445

TPS70448

TPS70451

TPS70458

3.3 V

1.2 V

1.5 V

1.8 V

2.5 V

HTSSOP-24 (PWP)

Tape and Reel, 2000

Tube, 60

Tape and Reel, 2000

Tube, 60

Tape and Reel, 2000

Tube, 60

Tape and Reel, 2000

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at ti.com.

(2) For fixed 1.20 V operation, tie FB to OUT.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

TPS704xx

UNIT

V

(2)

Input voltage range: V_IN1, V_IN2

Voltage range at EN1, EN2

–0.3 to +7

V

Output voltage range (V_OUT1, V_SENSE1

Output voltage range (V_OUT2, V_SENSE2

Maximum RESET, PG1, PG2 voltage

Maximum MR voltage

)

5.5

V

5.5

V

7

V

V_IN1

Internally limited

See Dissipation Ratings Table

–40 to +150

V

Peak output current

—

°C

kV

Continuous total power dissipation

Operating virtual junction temperature range, T_J

Storage temperature range, T_stg

ESD rating, HBM

–65 to +150

2

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are tied to network ground.

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TPS70445, TPS70448

TPS70451, TPS70458

TPS70402

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

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DISSIPATION RATINGS

DERATING

FACTOR

PACKAGE

AIR FLOW (CFM)

T_A≤ +25°C

T_A= +70°C

T_A= +85°C

0

3.067W

4.115W

30.67mW/°C

41.15mW/°C

1.687W

2.265W

1.227W

1.646W

PWP⁽¹⁾

250

(1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in ground

layer. For more information, refer to TI technical brief SLMA002.

RECOMMENDED OPERATING CONDITIONS

Over operating temperature range (unless otherwise noted).

MIN

2.7

0

MAX

6

UNIT

V

Input voltage, V_I⁽¹⁾(regulator 1 and 2)

Output current, I_O(regulator 1)

1

A

Output current, I_O(regulator 2)

0

2

A

Output voltage range (for adjustable option)

Operating virtual junction temperature, T_J

1.22

–40

5.5

+125

V

°C

(1) To calculate the minimum input voltage for maximum output current, use the following equation: V_I(min)= V_O(max)+ V_{DO(max load)}

.

4

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SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS

Over recommended operating junction temperature range (T_J= –40°C to +125°C), V_IN1or V_IN2= V_OUT(nom)+ 1 V, I_O= 1 mA,

EN = 0 V, C_OUT1= 22 mF, and C_OUT2= 47 mF (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

2.7 V < V_IN< 6 V,

T_J= +25°C

FB connected to V_O

1.22

Reference

voltage

2.7 V < V_IN< 6 V,

2.8 V < V_IN< 6 V,

3.5 V < V_IN< 6 V,

4.3 V < V_IN< 6 V,

FB connected to V_O

T_J= +25°C

1.196

1.176

1.47

1.244

1.224

1.2

1.5

1.8

2.5

3.3

185

1.2 V Output

(V_OUT2

)

T_J= +25°C

1.5 V Output

(V_OUT2

Output

)

(1) ,

1.53

1.836

2.55

V_O

voltage

V

(2)

1.8 V Output

(V_OUT2

)

1.764

2.45

2.5 V Output

(V_OUT2

)

3.3 V Output

(V_OUT2

)

3.234

3.366

(2)

Quiescent current (GND current) for

regulator 1 and regulator 2, EN1 = EN2

= 0 V⁽¹⁾

See

mA

(2)

See

250

0.1

V_O+ 1 V < V_IN≤ 6 V,

V_O+ 1 V < V_IN≤ 6 V

T_J= +25°C

T_J= +25°C⁽¹⁾

(1)

0.01

Output voltage line regulation (∆V_O/V_O)

for regulator 1 and regulator 2

%V

mV

(3)

Load regulation for V_{OUT 1}and V_OUT2

Output noise Regulator 1

1

79

V_n

voltage

(TPS70451)

BW = 300 Hz to 50 kHz,

V_OUT= 0 V

C_O= 33 mF, T_J= +25°C

mV_RMS

Regulator 2

77

Regulator 1

Regulator 2

1.75

3.8

2.2

4.5

Output current limit

A

Thermal shutdown junction temperature

+150

1

°C

mA

Regulator 1

Regulator 2

Regulator 1

EN1 = V_IN, EN2 = V_IN

f = 1 kHz

T_J= +25°C

2

I_I

Standby

(standby) current

10

Power-

T_J= +25°C⁽¹⁾

65

60

supply ripple

rejection

PSRR

dB

Regulator 2

f = 1 kHz

(TPS70451)

RESET Terminal

Minimum input voltage for valid RESET I_RESET= 300 mA,

V

_(RESET)≤ 0.8 V

1.0

120

1.3

160

0.4

1

V

ms

V

t _(RESET)

RESET pulse duration

80

Output low voltage

Leakage current

V_IN= 3.5 V,

I_(RESET)= 1 mA

0.15

V_(RESET)= 6 V

mA

(1) Minimum input operating voltage is 2.7 V or V_O(typ)+ 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output

current = 1 mA.

(2) I_O= 1 mA to 1 A for Regulator 1 and 1 mA to 2 A for Regulator 2.

(V_Imax- 2.7)

Line regulation (mV) = (%/V) x V_o

x 1000

100

[V_Imax- (V_o+ 1)]

(3) If V_O< 1.8 V then V_Imax= 6 V, V_Imin= 2.7 V:

Line regulation (mV) = (%/V) x V_o

x 1000

100

If V_O> 2.5 V then V_Imax= 6 V, V_Imin= V_O+ 1 V:

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TPS70451, TPS70458

TPS70402

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

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ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating junction temperature range (T_J= –40°C to +125°C), V_IN1or V_IN2= V_OUT(nom)+ 1 V,

I_O= 1 mA,

EN = 0 V, C_OUT1= 22 mF, and C_OUT2= 47 mF (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_IN1/V_IN2Terminal

UVLO threshold

2.4

2.65

V

UVLO hysteresis

110

mV

PG1/PG2 Terminal

Minimum input voltage for valid PGx

Trip threshold voltage

Hysteresis voltage

t_r(PGx)

I_(PGx)= 300 mA,

V_Odecreasing

Measured at V_O

V_(PGx)≤ 0.8 V

1.0

95

1.3

V

92

98 %V_OUT

%V_OUT

ms

0.5

30

Rising edge deglitch

V_IN= 2.7V,

Output low voltage

Leakage current

I_(PGx)= 1 mA

0.15

0.4

1

V

V_(PGx)= 6V

mA

EN1/EN2 Terminal

High-level ENx input voltage

Low-level ENx input voltage

Input current (ENx)

MR Terminal

2

–1

2

V

0.7

1

mA

High-level input voltage

Low-level input voltage

Pull-up current source

V_OUT1Terminal

V

0.7

6

mA

I_O= 1 A, V_IN1= 3.2 V

2 ms pulse width

V_OUT1= 1.5 V

T_J= +25°C

160

Dropout voltage⁽⁴⁾

mV

250

Peak output current

Discharge transistor current

V_OUT2Terminal

1.2

7.5

A

mA

Peak output current

Discharge transistor current

FB Terminal

2 ms pulse width

V_OUT2= 1.5 V

3

A

7.5

mA

Input current: TPS70402

FB = 1.8 V

1

mA

(4) Input voltage (V_IN1or V_IN2) = V_O(typ)– 100 mV. For 1.5-V, 1.8-V, and 2.5-V regulators, the dropout voltage is limited by input voltage

range. The 3.3-V regulator input is set to 3.2 V to perform this test.

6

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SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

DEVICE INFORMATION

Fixed Voltage Version

VIN1 (2 Pins)

V

(2 Pins)

OUT1

UVLO1

Comp

10kW

Current

Sense

-

VSENSE1

ENA_1

+

2.5 V

(see Note A)

-

+

ENA_1

Reference

V

ref

GND

Thermal

V

ref

Shutdown

PG1

-

VSENSE1

Rising Edge

Deglitch

+

0.95 x Vref

V

IN1

PG1

Comp

MR

RESET

120 ms

Delay

ENA_1

EN1

PG2

Comp

PG2

-

VSENSE2

Rising Edge

Deglitch

0.95 x Vref

+

ENA_2

V

ref

FB2

EN2

-

+

ENA_2

UVLO2

Comp

VSENSE2

+

2.5 V

Current

Sense

ENA_2

(see Note A)

10kW

-

V

(2 Pins)

V

(2 Pins)

OUT2

IN2

A. For most applications, V_SENSE1and V_SENSE2should be externally connected to V_OUT1and V_OUT2, respectively, as

close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the

Application Information section.

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SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

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Adjustable Voltage Version

V

(2 Pins)

VIN1 (2 Pins)

OUT1

UVLO1

Comp

Current

Sense

-

FB1

(see Note A)

ENA_1

+

2.5 V

-

+

ENA_1

Reference

V

ref

FB1

GND

Thermal

V

ref

Shutdown

PG1

-

FB1

Rising Edge

Deglitch

+

0.95 x Vref

V

IN1

PG1

Comp

MR

RESET

120 ms

Delay

ENA_1

EN1

PG2

Comp

PG2

-

FB2

Rising Edge

Deglitch

0.95 x Vref

+

ENA_2

V

ref

FB2

EN2

-

+

ENA_2

UVLO2

Comp

FB2

(see Note A)

+

2.5 V

Current

Sense

ENA_2

-

V (2 Pins)

OUT2

V

(2 Pins)

IN2

A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the

device. For other implementations, refer to FB terminals connection discussion in the Application Information

section.

8

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SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

RESET Timing Diagram

V

IN1

V

UVLO

V

UVLO

V

RES

(see Note A)

t

MR Input

t

RESET Output

120 ms

Delay

120 ms

Delay

Output

Undefined

t

NOTE A: V_RESis the minimum input voltage for a valid RESET. The symbol V_RESis not currently listed within EIA or JEDEC

standards for semiconductor symbology.

PG1 Timing Diagram

V

IN1

V

UVLO

V

UVLO

V

PG1

V

PG

(see Note A)

t

V

OUT1

V

IT+

(see Note B)

Threshold

Voltage

V

IT-

(see Note B)

t

PG1 Output

Output

PG1

Output

Undefined

t

NOTES A: V_PG1is the minimum input voltage for a valid PG. The symbol V_PG1is not currently listed within EIA or JEDEC

standards for semiconductor symbology.

NOTES B: V_IT-trip voltage is typically 5% lower than the output voltage (95%V_O). V_IT-to V_IT+is the hysteresis voltage.

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PG2 Timing Diagram (assuming V_IN1already powered up)

V

IN2

t

V

OUT2

V

IT+

(see Note A)

Threshold

Voltage

V

IT-

(see Note A)

t

PG2

Output

t

NOTE A: V_IT-trip voltage is typically 5% lower than the output voltage (95%V_O). V_IT-to V_IT+is the hysteresis voltage.

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

EN1

NO.

6

I

Active low enable for V_OUT1

Active low enable for V_OUT2

Ground

EN2

7

GND

9

—

GND/HEATSI

NK

1, 12, 13, 24

—

Ground/heatsink

MR

5

4, 17, 20

19

I

—

O

I

Manual reset input, active low, pulled up internally

No connection

NC

PG1

Open drain output, low when V_OUT1voltage is less than 95% of the nominal regulated voltage

Open drain output, low when V_OUT2voltage is less than 95% of the nominal regulated voltage

Open drain output, SVS (power-on reset) signal, active low

Input voltage of regulator 1

PG2

18

RESET

V_IN1

8

2, 3

V_IN2

10, 11

22, 23

14, 15

21

I

Input voltage of regulator 2

V_OUT1

V_OUT2

V_SENSE1/FB1

V_SENSE2/FB2

O

I

Output voltage of regulator 1

Output voltage of regulator 2

Regulator 1 output voltage sense/regulator 1 feedback for adjustable

Regulator 2 output voltage sense/regulator 2 feedback for adjustable

16

I

10

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Detailed Description

The TPS704xx low dropout regulator family provides dual regulated output voltages with independent enable

functions. These devices provide fast transient response and high accuracy with small output capacitors, while

drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good

(PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features

provide a complete power solution.

The TPS704xx, unlike many other LDOs, features very low quiescent current that remains virtually constant even

with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directly

proportional to the load current through the regulator (I_B= I_C/b). The TPS704xx uses a PMOS transistor to pass

current; because the gate of the PMOS is voltage-driven, operating current is low and stable over the full load

range.

Pin Functions

Enable (EN1, EN2)

The EN terminals are inputs that enable or shut down each respective regulator. If EN is at a voltage high signal,

the respective regulator is in shutdown mode. When EN goes to voltage low, the respective regulator is enabled.

Power-Good (PG1, PG2)

The PG terminals are open drain, active high output terminals that indicate the status of each respective

regulator. When V_OUT1reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When V_OUT2

reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance

state when its respective output voltage is pulled below 95% (that is, goes to an overload condition) of its

regulated voltage. The open drain outputs of the PG terminals require a pull-up resistor.

Manual Reset Pin

MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR

(RESET) occurs. The terminal has a 6-mA pull-up current to V_IN1; however, it is recommended that the pin be

pulled high to V_IN1when it is not used.

Sense (V_SENSE1, V_SENSE2

)

The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection

should be as short as possible. Internally, the sense terminal connects to high-impedance, wide-bandwidth

amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential

to route the sense connection in such a way as to minimize or avoid noise pickup. Adding RC networks between

sense terminals and V_OUTterminals to filter noise is not recommended because these networks can cause the

regulators to oscillate.

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FB1 and FB2

FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external

feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them

in such a way as to minimize or avoid noise pickup. Adding RC networks between FB terminals and V_OUT

terminals to filter noise is not recommended because these networks can cause the regulators to oscillate.

RESET Indicator

RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up,

RESET goes into a high impedance state (that is, logic high) after a 120-ms delay when both of the following

conditions are met. First, V_IN1must be above the undervoltage condition. Second, the manual reset (MR) pin

must be in a high impedance state. To monitor V_OUT1, the PG1 output pin can be connected to MR. To monitor

V_OUT2, the PG2 output pin can be connected to MR. If RESET is not used, it can be left floating.

V_IN1and V_IN2

V_IN1and V_IN2are inputs to each regulator. Internal bias voltages are powered by V_IN1

.

V_OUT1and V_OUT2

V_OUT1and V_OUT2are output terminals of each regulator.

12

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TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

vs Output current

vs Junction temperature

vs Frequency

Figure 1 and Figure 2

Figure 3 to Figure 4

Figure 5

V_O

Output voltage

Ground current

PSRR

Z_O

Power-supply rejection ratio

Output spectral noise density

Output impedance

Figure 6 to Figure 9

Figure 10 to Figure 13

Figure 14 to Figure 17

Figure 18 and Figure 19

Figure 20 and Figure 21

Figure 22 and Figure 23

Figure 24

vs Frequency

vs Temperature

vs Input voltage

Dropout voltage

Load transient response

Line transient response (V_OUT1

Line transient response (V_OUT2

Output voltage

)

Figure 25

V_O

vs Time (start-up)

vs Output current

Figure 26 and Figure 27

Figure 29 to Figure 32

Equivalent series resistance (ESR)

TPS70451

OUTPUT VOLTAGE

vs

TPS70451

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

3.33

3.32

3.31

3.30

1.815

1.81

V

T

= 2.8 V

IN2

V

T

= 4.3 V

IN1

= 25°C

J

= 25°C

J

V

OUT2

V

OUT1

1.805

1.8

1.795

3.29

3.28

3.27

1.79

1.785

0

500

1000

1500

2000

0

200

400

600

800

1000

I

- Output Current - mA

I

- Output Current - mA

O

Figure 1.

Figure 2.

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TYPICAL CHARACTERISTICS (continued)

TPS70451

OUTPUT VOLTAGE

vs

TPS70451

OUTPUT VOLTAGE

vs

JUNCTION TEMPERATURE

1.834

1.824

1.814

1.804

1.794

V

= 2.8 V

V

= 4.3 V

IN2

IN1

3.354

OUT2

OUT1

3.334

3.314

I

= 1 mA

O

I

= 2 A

O

3.294

I

= 1 mA

O

I

= 1 A

O

3.274

3.254

3.234

1.784

1.774

1.764

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T

- Junction Temperature - °C

J

T

- Junction Temperature - °C

J

Figure 3.

Figure 4.

TPS70451

GROUND CURRENT

vs

JUNCTION TEMPERATURE

210

Regulator 1 and Regulator 2

200

190

180

170

I

= 1 mA

OUT1

OUT2

I

= 1 A

= 2 A

OUT1

OUT2

160

150

-40 -25 -10

5

20 35 50 65 80 95 110 125

T

- Junction Temperature - °C

J

Figure 5.

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TYPICAL CHARACTERISTICS (continued)

TPS70451

POWER-SUPPLY REJECTION RATIO

vs

FREQUENCY

-10

-20

-30

-40

-50

-60

-70

-80

-90

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

V

I

= 4.3 V

IN1

V

I

= 4.3 V

IN1

= 3.3 V

OUT1

= 3.3 V

OUT1

= 1 A

= 10 mA

O

C

= 22 mF

C

= 22 mF

O

10

100

1 k

10 k

100 k

1 M

10

100

1 k

10 k

100 k

1 M

f - Frequency - Hz

Figure 6.

Figure 7.

TPS70451

POWER-SUPPLY REJECTION RATIO

vs

FREQUENCY

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

V

= 2.8 V

V

= 2.8 V

IN2

V

I

= 1.8 V

V

I

= 1.8 V

OUT2

= 2 A

= 10 mA

O

C

= 47 mF

C = 47 mF

O

10

100

1 k

10 k

100 k

1 M

10

100

1 k

10 k

100 k

1 M

f - Frequency - Hz

Figure 8.

Figure 9.

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TYPICAL CHARACTERISTICS (continued)

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

10

V

= 4.3 V

V

= 2.8 V

IN1

IN2

= 3.3 V

= 1.8 V

= 47 mF

OUT1

OUT2

C

I

= 22 mF

C

I

OUT1

OUT2

= 10 mA

O

T

= 25°C

T

= 25°C

J

1

0.1

0.01

100

1 k

10 k

100 k

100

1 k

10 k

100 k

f - Frequency - Hz

Figure 10.

Figure 11.

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

10

V

= 4.3 V

V

= 2.8 V

IN1

IN2

= 3.3 V

= 1.8 V

OUT1

OUT2

C

I

= 22 mF

C

I

= 47 mF

OUT1

OUT2

= 1 mA

= 2 A

O

T

= 25°C

T

= 25°C

J

1

0.1

0.01

100

0.01

100

1 k

10 k

100 k

1 k

10 k

100 k

f - Frequency - Hz

Figure 12.

Figure 13.

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TYPICAL CHARACTERISTICS (continued)

OUTPUT IMPEDANCE

vs

OUTPUT IMPEDANCE

vs

FREQUENCY

V

I

= 3.3 V

OUT1

V

I

= 3.3 V

OUT1

= 1 A

O

= 10 mA

O

C

= 22 mF

O

C

= 22 mF

O

1

0.1

0.01

10

100

1 k

10 k

100 k

1 M

10 M

10

100

1 k

10 k

100 k

1 M

10 M

f - Frequency - Hz

Figure 14.

Figure 15.

OUTPUT IMPEDANCE

vs

OUTPUT IMPEDANCE

vs

FREQUENCY

V

I

= 1.8 V

V

= 1.8 V

OUT2

= 10 mA

I

= 2 A

O

C

= 47 mF

C

= 47 mF

O

1

0.1

0.01

10

100

1 k

10 k

100 k

1 M

10 M

10

100

1 k

10 k

100 k

1 M

10 M

f - Frequency - Hz

Figure 16.

Figure 17.

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TYPICAL CHARACTERISTICS (continued)

TPS70451

DROPOUT VOLTAGE

vs

TPS70451

DROPOUT VOLTAGE

vs

TEMPERATURE

250

200

150

100

50

25

V

OUT1

= 3.2 V

IN1

20

15

I

= 1 A

O

I

= 100 mA

O

10

5

I

= 1 mA

O

I

= 10 mA

O

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T - Temperature - °C

Figure 18.

Figure 19.

TPS70402

DROPOUT VOLTAGE

vs

DROPOUT VOLTAGE

vs

INPUT VOLTAGE

300

V

I

V

I

OUT1

= 1 A

OUT2

= 2 A

O

250

200

250

200

T

= 125°C

J

T

= 125°C

J

T

= 25°C

J

T

= 25°C

J

150

100

50

150

100

50

T

= -40°C

J

T

= -40°C

J

0

2.5

0

2.5

3

3.5

4

4.5

5

5.5

3

3.5

4

4.5

5

5.5

V - Input Voltage - V

I

Figure 20.

Figure 21.

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TYPICAL CHARACTERISTICS (continued)

LOAD TRANSIENT RESPONSE

V

= 4.3 V

V

= 1.8 V

IN1

OUT2

V

= 3.3 V

1

I

= 2 A

2

1

OUT1

O

C

= 22 mF

C

= 47 mF

O

0.5

0

50

0

50

0

-50

-100

-50

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

t - Time - ms

Figure 22.

Figure 23.

LINE TRANSIENT RESPONSE

V

= 3.3 V

V

= 1.8 V

OUT2

OUT1

I

= 1 A

I = 2 A

O

5.3

4.3

3.8

2.8

O

C

= 22 mF

C = 47 mF

O

50

0

100

0

50

100

200

100

0

20 40 60 80 100 120 140 160 180 200

0

20 40 60 80 100 120 140 160 180 20

t - Time - ms

Figure 24.

Figure 25.

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TYPICAL CHARACTERISTICS (continued)

OUTPUT VOLTAGE AND ENABLE VOLTAGE

vs

TIME (START-UP)

4

3

V

= 3.3 V

OUT1

I

= 1 A

O

2

1

0

2

1

0

C

V

= 22 mF

O

= 4.3 V

IN1

EN2 = High

V

= 1.8 V

OUT2

I

= 2 A

O

C

V

= 47 mF

O

= 2.8 V

IN2

5

0

5

0

EN1 = High

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

t - Time - ms

Figure 26.

Figure 27.

To Load

V_IN

IN

OUT

+

C_OUT

R_L

EN

GND

ESR

Figure 28. Test Circuit for Typical Regions of Stability

20

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TYPICAL CHARACTERISTICS (continued)

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE⁽¹⁾

vs

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE⁽¹⁾

vs

OUTPUT CURRENT

10

V

= 3.3 V

V

= 3.3 V

OUT1

C

= 22 mF

C

= 220 mF

O

REGION OF INSTABILITY

1

0.1

50 mW

15 mW

0.01

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

I

- Output Current - A

I

- Output Current - A

O

Figure 29.

Figure 30.

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE⁽¹⁾

vs

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE⁽¹⁾

vs

OUTPUT CURRENT

10

REGION OF INSTABILITY

V

= 1.8 V

V

= 1.8 V

OUT2

C

= 47 mF

C

= 680 mF

O

1

0.1

50 mW

15 mW

0.01

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

I

- Output Current - A

I

- Output Current - A

O

Figure 31.

Figure 32.

⁽¹⁾Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any

series resistance added externally, and PWB trace resistance to C_O.

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THERMAL INFORMATION

Thermally-Enhanced TSSOP-24 (PWP— PowerPAD™)

The thermally-enhanced PWP package is based on the 24-pin TSSOP, but includes a thermal pad [see

Figure 33(c)] to provide an effective thermal contact between the IC and the printed wiring board (PWB).

Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down

TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications.

These packages, however, suffer from several shortcomings: they do not address the very low profile

requirements (<2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough to

accommodate increasing integration. On the other hand, traditional low-power surface-mount packages require

power-dissipation derating that severely limits the usable range of many high-performance analog circuits.

The PWP package (thermally-enhanced TSSOP) combines fine-pitch surface-mount technology with thermal

performance comparable to much larger power packages.

The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size and

limited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths

that remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending)

and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad

is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultrathin, fine-pitch,

surface-mount package can be reliably achieved.

DIE

Side View (a)

Thermal

Pad

DIE

End View (b)

Bottom View (c)

Figure 33. Views of Thermally-Enhanced PWP Package

Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal

considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface),

which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference

Figure 35(a), 8 cm²of copper heat sink and natural convection). Increasing the heat-sink size increases the

power dissipation range for the component. The power dissipation limit can be further improved by adding airflow

to a PWB/IC assembly (see Figure 34 and Figure 35). The line drawn at 0.3 cm²in Figure 34 and Figure 35

indicates performance at the minimum recommended heat-sink size, illustrated in Figure 36.

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The thermal pad is directly connected to the substrate of the IC, which for the TPS704xx series is a secondary

electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane or

left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary

electrical connection for a given terminal which is not always ground. The PWP package provides up to 24

independent leads that can be used as inputs and outputs (Note: leads 1, 12, 13, and 24 are internally

connected to the thermal pad and the IC substrate).

THERMAL RESISTANCE

vs COPPER HEATSINK AREA

150

125

100

Natural Convection

50 ft/min

100 ft/min

150 ft/min

200 ft/min

75

50

25

250 ft/min

300 ft/min

0 0.3

1

2

3

4

5

6

7

8

2

Copper Heatsink Area - cm

Figure 34.

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3.5

T

A

= 25°C

T

A

= 55°C

300 ft/min

3

2.5

2

3

2.5

2

150 ft/min

300 ft/min

150 ft/min

Natural Convection

1.5

Natural Convection

1

0.5

0

1

0.5

0

2

4

6

2

8

0

2

4

6

8

0.3

2

Copper Heatsink Size - cm

(a)

(b)

3.5

T

A

= 105°C

3

2.5

2

1.5

1

150 ft/min

300 ft/min

Natural Convection

0.5

0

0.3

2

4

6

2

8

Copper Heatsink Size - cm

(c)

Figure 35. Power Ratings of the PWP Package at Ambient Temperatures of +25°C, +55°C, and +105°C

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Figure 36 is an example of a thermally-enhanced PWB layout for use with the new PWP package. This board

configuration was used in the thermal experiments that generated the power ratings shown in Figure 34 and

Figure 35. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. R_qJA

for this assembly is illustrated in Figure 34 as a function of heat-sink area. A family of curves is included to

illustrate the effect of airflow introduced into the system.

Heatsink Area

1 oz Copper

Board thickness

Board size

62 mils

3.2 in ´ 3.2 in

FR4

Board material

Copper trace/heat sink 1 oz

Exposed pad mounting 63/67 tin/lead solder

Figure 36. PWB Layout (Including Copper Heatsink Area) for Thermally-Enhanced PWP Package

From Figure 34, R_qJAfor a PWB assembly can be determined and used to calculate the maximum

power-dissipation limit for the component/PWB assembly, with the equation:

T_Jmax- T_A

P_D(max)

=

R_qJA(system)

where:

•

T_Jmaxis the maximum specified junction temperature (+150°C absolute maximum limit, +125°C recommended

operating limit) and T_Ais the ambient temperature.

(1)

P_D(max)should then be applied to the internal power dissipated by the TPS704xx regulator. The equation for

calculating total internal power dissipation of the TPS704xx is:

I_Q

P_D(total)

=

V_IN1- V_OUT1´ I_OUT1+ V_IN1

(

´

+ V_IN2- V_OUT2´ I_OUT2+ V_IN2´

(

2

(2)

Since the quiescent current of the TPS704xx is very low, the second term is negligible, further simplifying the

equation to:

P_D(total)

=

V_IN1- V_OUT1´ I_OUT1

(

+ V_IN2- V_OUT2´ I_OUT2

(

(3)

For the case where T_A= +55°C, airflow = 200 ft/min, copper heat-sink area = 4 cm², the maximum

power-dissipation limit can be calculated. First, from Figure 34, we find the system R_qJAis +50°C/W; therefore,

the maximum power-dissipation limit is:

T_Jmax- T_A

+125°C - 55°C

+50°C/W

P_D(max)

=

= 1.4 W

R_qJA(system)

(4)

=

If the system implements a TPS704xx regulator, where V_IN1= 5.0V, V_IN2= 2.8 V, I_OUT1= 500 mA, and I_OUT2

800 mA, the internal power dissipation is:

P_D(total)

=

V_IN1- V_OUT1´ I_OUT1

+ V_IN2- V_OUT2´ I_OUT2

(

= (5.0 - 3.3) ´ 0.5 + (2.8 - 1.8) ´ 0.8 = 1.25 W

(

(5)

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Comparing P_D(total)with P_D(max)reveals that the power dissipation in this example does not exceed the calculated

limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit by

increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing

the input voltage or the load current. In either case, the above calculations should be repeated with the new

system parameters. This parameter is measured with the recommended copper heat sink pattern on a 4-layer

PWB, 2 oz. copper traces on 4-in × 4-in ground layer. Simultaneous and continuous operation of both regulator

outputs at full load may exceed the power dissipation rating of the PWP package.

Mounting Information

The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The

thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted.

Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The data

included in Figure 34 and Figure 36 are for soldered connections with voiding between 20% and 50%. The

thermal analysis shows no significant difference resulting from the variation in voiding percentage.

Figure 37 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink area

is also illustrated. This is simply a copper plane under the body extent of the package, including metal routed

under terminals 1, 12, 13, and 24.

Minimum Recommended

Heatsink Area

Location of Exposed

Thermal Pad on

PWP Package

Figure 37. PWP Package Land Pattern

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APPLICATION INFORMATION

TPS704xxPWP

(Fixed Output Option)

V_OUT1

Sequencing Timing Diagrams

This section provides a number of timing diagrams

showing how this device functions in different

configurations.

V_IN

V_OUT1

V_IN1

22 mF

0.22 mF

V_SENSE1

250 kW

Application condition: V_IN1and V_IN2are tied to the

same fixed input voltage greater than V_UVLO. PG2 is

tied to MR.

PG1

MR

EN1 and EN2 are initially high; therefore, both

regulators are off, and PG1 and PG2 (tied to MR) are

at logic low. Since MR is at logic low, RESET is also

at logic low. When EN1 is taken to logic low, V_OUT1

turns on. Later, when EN2 is taken to logic low, V_OUT2

turns on. When V_OUT1reaches 95% of its regulated

output voltage, PG1 goes to logic high. When V_OUT2

reaches 95% of its regulated output voltage, PG2

(tied to MR) goes to logic high. When V_IN1is greater

than V_UVLOand M R (tied to PG2) is at logic high,

RESET is pulled to logic high after a 120-ms delay.

When EN1 and EN2 are returned to logic high, both

devices power down and both PG1, PG2 (tied to

MR2), and RESET return to logic low.

V_IN2

250 kW

0.22 mF

RESET

PG2

RESET

PG2

EN1

<0.7 V

EN2

EN1

EN2

>2 V

V_SENSE2

V_OUT2

<0.7 V

47 mF

EN2

EN1

95%

V_OUT2

95%

V_OUT1

PG2

PG1

MR

(PG2 tied to MR)

RESET

t₁

120 ms

NOTES: A. t₁: Time at which V_INis greater than V_UVLOand MR is logic high.

B. The timing diagram is not drawn to scale.

Figure 38. Timing When V_OUT1Is Enabled Before V_OUT2

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Application condition: V_IN1and V_IN2are tied to the

same fixed input voltage greater than V_UVLO. MR is

initially logic high but is eventually toggled.

TPS704xxPWP

(Fixed Output Option)

V_OUT1

V_IN

V_IN1

V_OUT1

EN1 and EN2 are initially high; therefore, both

regulators are off, and PG1 and PG2 are at logic low.

Since V_IN1is greater than V_UVLOand MR is at logic

high, RESET is also at logic high. When EN2 is taken

to logic low, V_OUT2turns on. Later, when EN1 is taken

to logic low, V_OUT1turns on. When V_OUT2reaches

95% of its regulated output voltage, PG2 goes to

logic high. When V_OUT1reaches 95% of its regulated

output voltage, PG1 goes to logic high. When MR is

taken to logic low, RESET is taken low. When MR

returns to logic high, RESET returns to logic high

after a 120-ms delay.

0.22 mF

V_SENSE1

250 kW

22 mF

250 kW

V_IN2

0.22 mF

RESET

PG2

MR

EN1

EN2

2 V

MR

>2 V

V_SENSE2

0.7 V

<0.7 V

EN2

V_OUT2

<0.7 V

47 mF

EN2

EN1

V_OUT2

95%

V_OUT1

PG2

PG1

MR

RESET

t₁

120 ms

NOTES: A. t₁: Time at which V_INis greater than V_UVLOand MR is logic high.

B. The timing diagram is not drawn to scale.

Figure 39. Timing When MR is Toggled

28

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TPS70451, TPS70458

TPS70402

www.ti.com

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

Application condition: V_IN1and V_IN2are tied to

same fixed input voltage greater than V_UVLO. PG1 is

tied to MR.

TPS704xxPWP

(Fixed Output Option)

V_OUT1

V_IN

V_OUT1

V_IN1

EN1 and EN2 are initially high; therefore, both

regulators are off, and PG1 (tied to MR) and PG2 are

at logic low. Since MR is at logic low, RESET is also

at logic low. When EN2 is taken to logic low, V_OUT2

turns on. Later, when EN1 is taken to logic low, V_OUT1

turns on. When V_OUT2reaches 95% of its regulated

output voltage, PG2 goes to logic high. When V_OUT1

reaches 95% of its regulated output voltage, PG1

goes to logic high. When V_IN1is greater than V_UVLO

and MR (tied to PG2) is at logic high, RESET is

pulled to logic high after a 120-ms delay. When a

fault on V_OUT1causes it to fall below 95% of its

regulated output voltage, PG1 (tied to MR) goes to

logic low. Since MR is logic low, RESET goes to logic

low. V_OUT2is unaffected.

0.22 mF

22 mF

V_SENSE1

250 kW

PG1

MR

250 kW

V_IN2

0.22 mF

RESET

PG2

EN1

>2 V

V_SENSE2

<0.7 V

EN2

V_OUT2

<0.7 V

47 mF

EN2

EN1

V_OUT2

95%

V_OUT1

FAULT ON V_OUT1

PG2

PG1

MR

(PG1 tied to MR)

RESET

t₁

120 ms

NOTES: A. t₁: Time at which V_INis greater than V_UVLOand MR is logic high.

B. The timing diagram is not drawn to scale.

Figure 40. Timing When There is a Fault on V_OUT1

Submit Documentation Feedback

29

TPS70445, TPS70448

TPS70451, TPS70458

TPS70402

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

www.ti.com

APPLICATION INFORMATION

Input Capacitor

For a typical application, a ceramic input bypass capacitor (0.22 mF to 1 mF) is recommended. This capacitor

should be as close to the input pins as possible. Due to the impedance of the input supply, large transient

currents cause the input voltage to droop. If this droop causes the input voltage to drop below the UVLO

threshold, the device turns off. Therefore, it is recommended to place a larger capacitor in parallel with the

ceramic bypass capacitor at the regulator input. The size of this capacitor depends on the output current, the

response time of the main power supply, and the main power supply distance to the regulator. At a minimum, the

capacitor should be sized to ensure that the input voltage does not drop below the minimum UVLO threshold

voltage during normal operating conditions.

Output Capacitor

As with most LDO regulators, the TPS704xx requires an output capacitor connected between OUT and GND to

stabilize the internal control loop. The minimum recommended capacitance value for V_OUT1is 22 mF and the ESR

(equivalent series resistance) must be between 50 mΩ and 800 mΩ. The minimum recommended capacitance

value for V_OUT2is 47 mF and the ESR must be between 50 mΩ and 2 Ω. Solid tantalum electrolytic, aluminum

electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described

above. Larger capacitors provide a wider range of stability and better load transient response. Table 1 gives a

partial listing of surface-mount capacitors suitable for use with the TPS704xx for fast transient response

applications.

This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for user

applications. When necessary to achieve low height requirements along with high output current and/or high load

capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.

Table 1. Partial Listing of TPS704xx-Compatible Surface-Mount Capacitors

VALUE

680 mF

470 mF

150 mF

220 mF

100 mF

68 mF

MANUFACTURER

Kemet

MFR PART NO.

T510X6871004AS

4TPB470M

Sanyo

4TPC150M

Sanyo

2R5TPC220M

10TPC68M

Sanyo

68 mF

Kemet

T495D6861006AS

T495D4761010AS

T495C3361016AS

T495C2261010AS

47 mF

Kemet

33 mF

Kemet

22 mF

Kemet

30

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TPS70451, TPS70458

TPS70402

www.ti.com

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

Programming the TPS70402 Adjustable LDO Regulator

The output voltage of the TPS70402 adjustable regulators is programmed using external resistor dividers as

shown in Figure 41.

Resistors R1 and R2 should be chosen for approximately a 50-mA divider current. Lower value resistors can be

used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage

currents at the sense terminal increase the output voltage error. The recommended design procedure is to

choose R2 = 30.1 kΩ to set the divider current at approximately 50 mA, and then calculate R1 using Equation 6:

V_OUT

R1 =

- 1 ´ R2

(

V_REF

(6)

where:

•

V_REF= 1.224 V typ (the internal reference voltage)

OUTPUT VOLTAGE

PROGRAMMING GUIDE

TPS70402

OUTPUT

VOLTAGE

V

I

R1

R2

UNIT

IN

0.1 mF

2.5 V

3.3 V

3.6 V

31.6

51.1

59.0

30.1

kW

>2.0 V

EN

OUT

FB

V

O

<0.7 V

+

R1

GND

R2

Figure 41. TPS70402 Adjustable LDO Regulator Programming

Regulator Protection

Both TPS704xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input

voltage drops below the output voltage (for example, during power-down). Current is conducted from the output

to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be

appropriate.

The TPS704xx also features internal current limiting and thermal protection. During normal operation, the

TPS704xx regulator 1 limits output current to approximately 1.75 A (typ) and regulator 2 limits output current to

approximately 3.8 A (typ). When current limiting engages, the output voltage scales back linearly until the

overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be

taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds

+150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below +130°C (typ),

regulator operation resumes.

Submit Documentation Feedback

31

TPS70445, TPS70448

TPS70451, TPS70458

TPS70402

SLVS307F –SEPTEMBER 2000–REVISED APRIL 2010

www.ti.com

REVISION HISTORY

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (February 2010) to Revision F

Page

•

Changed Tube transport media, quatity values from 70 to 60 in Ordering Information table .............................................. 3

Changes from Revision D (December, 2007) to Revision E

Page

•

Corrected pin description for pin 21 in pinout drawing ......................................................................................................... 1

Updated Dissipation Ratings table values ............................................................................................................................ 4

Deleted falling edge delay specification ................................................................................................................................ 6

Updated Fixed Voltage Version block diagram .................................................................................................................... 7

Updated Adjustable Voltage Version block diagram ............................................................................................................ 8

32

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PACKAGE OPTION ADDENDUM

www.ti.com

16-Apr-2010

PACKAGING INFORMATION

Orderable Device

TPS70402PWP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

24

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS70402PWPG4

TPS70402PWPR

TPS70402PWPRG4

TPS70445PWP

HTSSOP

PWP

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS70445PWPG4

TPS70445PWPR

TPS70445PWPRG4

TPS70448PWP

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS70448PWPG4

TPS70448PWPR

TPS70448PWPRG4

TPS70451PWP

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS70451PWPG4

TPS70451PWPR

TPS70451PWPRG4

TPS70458PWP

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TPS70458PWPG4

TPS70458PWPR

TPS70458PWPRG4

60 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

16-Apr-2010

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS70402PWPR

TPS70445PWPR

TPS70448PWPR

TPS70451PWPR

TPS70458PWPR

HTSSOP PWP

24

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS70402PWPR

TPS70445PWPR

TPS70448PWPR

TPS70451PWPR

TPS70458PWPR

HTSSOP

PWP

24

2000

367.0

38.0

Pack Materials-Page 2

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厂商	型号	描述	页数
HONEYWELL	4TP1-21	[ Rocker Switch, ROCKER SWITCH, 4PST, LATCHED, PANEL MOUNT ]	1 页
HONEYWELL	4TP1-3	[ Rocker Switch, 4PDT, Latched, Screw Terminal, Rocker Actuator, Panel Mount ]	3 页
HONEYWELL	4TP1-4	[ Rocker Switch, 4PDT, Momentary, Screw Terminal, Rocker Actuator, Panel Mount ]	1 页
HONEYWELL	4TP1-5	[ Rocker Switch, 4PDT, Latched And Momentary, Screw Terminal, Rocker Actuator, Panel Mount ]	1 页
HONEYWELL	4TP1-51	[ Rocker Switch, 4PDT, Momentary, Screw Terminal, Rocker Actuator, Panel Mount ]	1 页
HONEYWELL	4TP1-6	[ Rocker Switch, 4PST, Momentary, Screw Terminal, Rocker Actuator, Panel Mount ]	1 页
HONEYWELL	4TP1-61	[ Rocker Switch, 4PST, Momentary, Screw Terminal, Rocker Actuator, Panel Mount ]	1 页
HONEYWELL	4TP1-7	[ Rocker Switch, 4PDT, Momentary, Screw Terminal, Rocker Actuator, Panel Mount, ]	3 页
HONEYWELL	4TP1-70	[ Rocker Switch, 4PDT, Latched And Momentary, Screw Terminal, Rocker Actuator, Panel Mount ]	3 页
HONEYWELL	4TP1-8	[ Rocker Switch, 4PDT, Momentary, Screw Terminal, Rocker Actuator, Panel Mount ]	1 页