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LY61256RL-15LLE

型号：

LY61256RL-15LLE

描述：

32K ×8位高速CMOS SRAM[ 32K X 8 BIT HIGH SPEED CMOS SRAM ]

品牌：

LYONTEK[ Lyontek Inc. ]

页数：

13 页

PDF大小：

232 K

下载PDF手册
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
REVISION HISTORY  
Revision  
Rev. 1.0  
Rev. 1.1  
Rev. 1.2  
Rev. 1.3  
Rev. 1.4  
Description  
Initial Issue  
Issue Date  
Jul.25.2004  
Sep.21.2004  
Aug.18.2005  
Mar.26.2008  
Feb.2.2009  
Delete Icc1/ ISB Spec.  
Adding Skinny P-DIP  
Revised STSOP Package Outline Dimension  
Revised VTERM to VT1 and VT2  
Revised Test Condition of ISB1/IDR  
Added LL Spec.  
Rev. 1.5  
Revised Test Condition of ICC  
Apr.17.2009  
FEATURES ORDERING INFORMATION  
Revised  
&
Lead free and green package available to Green package  
available  
ABSOLUTE MAXIMUN RATINGS  
Deleted TSOLDER in  
ORDERING INFORMATION  
Added packing type in  
Rev. 1.6  
Rev. 1.7  
May.7.2010  
Aug.25.2010  
PACKAGE OUTLINE DIMENSION  
Revised  
Revised  
Revised  
in page 10  
ORDERING INFORMATION  
in page 11  
PACKAGE OUTLINE DIMENSION  
in page 9  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
0
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
FEATURES  
GENERAL DESCRIPTION  
The LY61256 is a 262,144-bit high speed CMOS  
static random access memory organized as 32,768  
words by 8 bits. It is fabricated using very high  
performance, high reliability CMOS technology. Its  
standby current is stable within the range of  
operating temperature.  
„ Fast access time : 8/10/12/15ns  
„ Low power consumption:  
Operating current : 110/100/90/80mA (TYP.)  
Standby current : 1mA (TYP.)  
2μA (TYP.) LL-version  
„ Single 5V power supply  
„ All inputs and outputs TTL compatible  
„ Fully static operation  
„ Tri-state output  
„ Data retention voltage : 2.0V (MIN.)  
„ Green package available  
„ Package : 28-pin 300 mil SOJ  
28-pin 300 mil Skinny P-DIP  
28-pin 8mm x 13.4mm STSOP  
The LY61256 is well designed for high speed  
system application. Easy expansion is provided by  
using an active LOW Chip Enable(CE#). The active  
LOW Write Enable(WE#) controls both writing and  
reading of the memory.  
The LY61256 operates from a single power  
supply of 5V and all inputs and outputs are fully TTL  
compatible  
PRODUCT FAMILY  
Power Dissipation  
Speed  
Product  
Family  
LY61256  
Operating  
Temperature  
0 ~ 70℃  
Vcc Range  
Standby(ISB1,TYP.) Operating(Icc,TYP.)  
4.5 ~ 5.5V  
4.5 ~ 5.5V  
4.5 ~ 5.5V  
4.5 ~ 5.5V  
4.5 ~ 5.5V  
4.5 ~ 5.5V  
8/10/12/15ns  
8/10/12/15ns  
8/10/12/15ns  
8/10/12/15ns  
8/10/12/15ns  
8/10/12/15ns  
1mA  
1mA  
110/100/90/80mA  
110/100/90/80mA  
110/100/90/80mA  
110/100/90/80mA  
110/100/90/80mA  
110/100/90/80mA  
-20 ~ 80℃  
-40 ~ 85℃  
0 ~ 70℃  
LY61256(E)  
LY61256(I)  
1mA  
LY61256(LL)  
LY61256(LLE)  
LY61256(LLI)  
2μA(LL)  
2μA(LL)  
2μA(LL)  
-20 ~ 80℃  
-40 ~ 85℃  
FUNCTIONAL BLOCK DIAGRAM  
PIN DESCRIPTION  
SYMBOL  
DESCRIPTION  
Address Inputs  
Vcc  
Vss  
A0 - A14  
DQ0 – DQ7 Data Inputs/Outputs  
32Kx8  
A0-A14  
DECODER  
MEMORY ARRAY  
CE#  
WE#  
OE#  
VCC  
Chip Enable Input  
Write Enable Input  
Output Enable Input  
Power Supply  
VSS  
Ground  
I/O DATA  
CIRCUIT  
DQ0-DQ7  
COLUMN I/O  
CE#  
WE#  
OE#  
CONTROL  
CIRCUIT  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
1
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
PIN CONFIGURATION  
A14  
A12  
A7  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
Vcc  
WE#  
A13  
A8  
3
OE#  
A11  
A9  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
A10  
CE#  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
Vss  
I/O3  
I/O2  
I/O1  
A0  
A6  
4
A5  
5
A9  
A8  
A4  
6
A11  
OE#  
A10  
CE#  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
A13  
WE#  
Vcc  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A3  
7
LY61256  
A2  
8
A1  
9
A0  
10  
11  
12  
13  
14  
A1  
A2  
I/O1  
I/O2  
I/O3  
Vss  
STSOP  
Skinny P-DIP/SOJ  
ABSOLUTE MAXIMUN RATINGS*  
PARAMETER  
SYMBOL  
VT1  
RATING  
-0.5 to 6.5  
UNIT  
V
Voltage on VCC relative to VSS  
Voltage on any other pin relative to VSS  
VT2  
-0.5 to VCC+0.5  
0 to 70(C grade)  
-20 to 80(E grade)  
-40 to 85(I grade)  
-65 to 150  
V
℃
Operating Temperature  
TA  
℃
W
Storage Temperature  
Power Dissipation  
DC Output Current  
TSTG  
PD  
1
IOUT  
50  
mA  
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress  
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this  
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.  
TRUTH TABLE  
CE#  
OE#  
WE#  
SUPPLY CURRENT  
MODE  
I/O OPERATION  
H
X
X
Standby  
High-Z  
ISB1  
ICC  
ICC  
ICC  
L
L
L
H
L
H
H
L
Output Disable  
Read  
High-Z  
DOUT  
DIN  
X
Write  
Note: H = VIH, L = VIL, X = Don't care.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
2
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
DC ELECTRICAL CHARACTERISTICS  
SYMBOL  
TEST CONDITION  
MIN.  
4.5  
2.4  
- 0.5  
- 1  
TYP. *4 MAX.  
UNIT  
PARAMETER  
Supply Voltage  
VCC  
5.0  
5.5  
VCC+0.5  
0.8  
V
V
V
*1  
Input High Voltage  
Input Low Voltage  
Input Leakage Current  
Output Leakage  
Current  
VIH  
VIL  
-
-
-
*2  
ILI  
V
V
CC ≧ VIN ≧ VSS  
CC ≧ VOUT ≧ VSS,  
Output Disabled  
IOL = 8mA  
1
A
µ
ILO  
- 1  
-
1
A
µ
Output High Voltage  
Output Low Voltage  
VOH IOH = -4mA  
VOL  
2.4  
-
-
-
V
V
-
-
-
-
-
-
0.4  
190  
180  
160  
140  
5
110  
100  
90  
80  
1
-8  
-10  
-12  
-15  
mA  
mA  
mA  
mA  
mA  
Cycle time = Min.  
CE# = VIL , II/O = 0mA  
Others at VIL or VIH  
Average Operating  
Power supply Current  
ICC  
CE# ≧VCC - 0.2V,  
CE# ≧VCC - 0.2V,  
Others at 0.2V or VCC-0.2V  
Normal  
Standby Power  
Supply Current  
ISB1  
LL  
-
2
50  
A
µ
Notes:  
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.  
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.  
3. Over/Undershoot specifications are characterized, not 100% tested.  
4. Typical values are included for reference only and are not guaranteed or tested.  
℃
Typical valued are measured at VCC = VCC(TYP.) and TA = 25  
CAPACITANCE (TA = 25℃, f = 1.0MHz)  
PARAMETER  
Input Capacitance  
Input/Output Capacitance  
SYMBOL  
CIN  
MIN.  
-
-
MAX  
6
8
UNIT  
pF  
pF  
CI/O  
Note : These parameters are guaranteed by device characterization, but not production tested.  
AC TEST CONDITIONS  
Input Pulse Levels  
0.2V to VCC - 0.2V  
Input Rise and Fall Times  
Input and Output Timing Reference Levels  
Output Load  
3ns  
1.5V  
CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
3
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
AC ELECTRICAL CHARACTERISTICS  
(1) READ CYCLE  
PARAMETER  
SYM.  
UNIT  
LY61256-8 LY61256-10 LY61256-12 LY61256-15  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
Read Cycle Time  
Address Access Time  
Chip Enable Access Time  
Output Enable Access Time  
Chip Enable to Output in Low-Z  
Output Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Disable to Output in High-Z  
Output Hold from Address Change  
tRC  
tAA  
8
-
-
-
8
8
4
-
10  
-
-
-
10  
10  
5
-
-
5
5
-
12  
-
-
-
12  
12  
6
-
-
6
6
-
15  
-
-
-
15  
15  
7
-
-
7
7
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tACE  
tOE  
tCLZ  
tOLZ  
tCHZ  
tOHZ  
tOH  
-
-
-
-
*
*
*
*
2
0
-
-
3
2
0
-
-
3
3
0
-
-
3
4
0
-
-
3
-
4
4
-
(2) WRITE CYCLE  
PARAMETER  
SYM.  
UNIT  
LY61256-8 LY61256-10 LY61256-12 LY61256-15  
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.  
Write Cycle Time  
tWC  
8
6.5  
6.5  
0
6.5  
0
5
0
1.5  
-
-
-
-
-
-
-
-
-
-
10  
8
8
0
8
0
6
0
2
-
-
-
-
-
-
-
-
-
-
12  
10  
10  
0
9
0
7
0
3
-
-
-
-
-
-
-
-
-
-
15  
12  
12  
0
10  
0
8
0
4
-
-
-
-
-
-
-
-
-
-
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Enable to End of Write  
Address Set-up Time  
Write Pulse Width  
Write Recovery Time  
Data to Write Time Overlap  
Data Hold from End of Write Time  
Output Active from End of Write  
Write to Output in High-Z  
tAW  
tCW  
tAS  
tWP  
tWR  
tDW  
tDH  
tOW  
*
*
tWHZ  
5
6
7
*These parameters are guaranteed by device characterization, but not production tested.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
4
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
TIMING WAVEFORMS  
READ CYCLE 1 (Address Controlled) (1,2)  
tRC  
Address  
Dout  
tAA  
tOH  
Previous Data Valid  
Data Valid  
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)  
tRC  
Address  
tAA  
CE#  
tACE  
OE#  
tOE  
tOLZ  
tOH  
tOHZ  
tCHZ  
tCLZ  
High-Z  
Dout  
High-Z  
Data Valid  
Notes :  
1.WE# is high for read cycle.  
2.Device is continuously selected OE# = low, CE# = low.  
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.  
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
5
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)  
tWC  
Address  
tAW  
CE#  
tCW  
tAS  
tWP  
tWR  
WE#  
Dout  
Din  
tWHZ  
TOW  
High-Z  
(4)  
(4)  
tDW  
tDH  
Data Valid  
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)  
tWC  
Address  
tAW  
CE#  
tAS  
tWR  
tCW  
tWP  
WE#  
Dout  
Din  
tWHZ  
High-Z  
(4)  
tDW  
tDH  
Data Valid  
Notes :  
1.WE#, CE# must be high during all address transitions.  
2.A write occurs during the overlap of a low CE#, low WE#.  
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be  
placed on the bus.  
4.During this period, I/O pins are in the output state, and input signals must not be applied.  
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.  
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
6
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
SYMBOL  
TEST CONDITION  
MIN. TYP. MAX. UNIT  
VCC for Data Retention  
VDR CE# ≧ VCC - 0.2V  
CC = 2.0V  
2.0  
-
5.5  
V
V
Normal  
LL  
-
0.6  
3
mA  
CE# ≧ VCC - 0.2V  
Data Retention Current  
IDR  
VCC = 2.0V  
CE# ≧ VCC - 0.2V  
Others at 0.2V or VCC-0.2V  
See Data Retention  
Waveforms (below)  
-
0.5  
20  
A
µ
Chip Disable to Data  
Retention Time  
Recovery Time  
tCDR  
tR  
0
-
-
-
-
ns  
ns  
tRC  
*
tRC = Read Cycle Time  
*
DATA RETENTION WAVEFORM  
VDR ≧ 2.0V  
Vcc(min.)  
Vcc  
Vcc(min.)  
tCDR  
tR  
VIH  
CE# ≧ Vcc-0.2V  
VIH  
CE#  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
7
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
PACKAGE OUTLINE DIMENSION  
28 pin 300 mil PDIP Package Outline Dimension  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
8
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
28-pin 300 mil SOJ Package Outline Dimension  
28  
15  
1
14  
A2  
X
XX  
C
L
UNIT  
INCH(REF)  
MM(BASE)  
SYM.  
A
A1  
A2  
B
0.140(MAX)  
0.025(MIN)  
3.556(MAX)  
0.635(MIN)  
±
2.540 0.381  
±
0.100 0.015  
±
±
0.457 0.102  
0.018 0.004  
B1  
c
±
±
0.711 0.102  
±
0.254 0.102  
0.028 0.004  
±
0.010 0.004  
D
E
±
±
18.03 0.508  
±
8.560 0.254  
0.710 0.020  
±
0.337 0.010  
E1  
e
±
±
7.620 0.127  
±
1.270 0.152  
0.300 0.005  
±
0.050 0.006  
L
±
±
0.087 0.010  
2.210 0.254  
S
Y
0.045(MAX)  
0.004(MAX)  
1.143(MAX)  
0.102(MAX)  
Note : 1.S/E/D dimension is not including mold flash.  
2.The end flash in package lengthwise is not more than 10 mils each side.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
9
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
28 pin 8x13.4mm STSOP Package Outline Dimension  
HD  
c
L
12° (2x)  
12° (2x)  
1
28  
14  
15  
"A"  
y
Seating Plane  
D
12° (2X)  
14  
15  
GAUGE PLANE  
0
SEATING PLANE  
12° (2X)  
L
1
28  
L1  
"A" DATAIL VIEW  
DIMENSIONS IN MILLIMETERS  
DIMENSIONS IN INCHES  
SYMBOLS  
MIN  
1.00  
0.05  
0.91  
0.17  
0.07  
13.20  
11.60  
7.80  
-
0.30  
0.675  
0.00  
0°  
NOM  
1.10  
-
MAX  
1.20  
0.15  
1.05  
0.27  
0.23  
13.60  
12.00  
8.20  
-
MIN  
NOM  
0.043  
-
MAX  
A
A1  
A2  
b
c
HD  
D
E
e
L
L1  
Y
0.040  
0.002  
0.036  
0.007  
0.003  
0.520  
0.457  
0.307  
-
0.012  
0.027  
0.000  
0°  
0.047  
0.006  
0.041  
0.011  
0.009  
0.535  
0.472  
0.323  
-
1.00  
0.22  
0.15  
13.40  
11.80  
8.00  
0.55  
0.50  
-
0.039  
0.009  
0.006  
0.528  
0.465  
0.315  
0.0216  
0.020  
-
0.70  
-
0.028  
-
-
3°  
0.076  
5°  
-
3°  
0.003  
5°  
Θ
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
10  
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
ORDERING INFORMATION  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
11  
®
LY61256  
32K X 8 BIT HIGH SPEED CMOS SRAM  
Rev. 1.7  
THIS PAGE IS LEFT BLANK INTENTIONALLY.  
Lyontek Inc. reserves the rights to change the specifications and products without notice.  
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.  
TEL: 886-3-6668838  
FAX: 886-3-6668836  
12  
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