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CYRF6936

WirelessUSB™ LP 2.4 GHz Radio SoC

■ Battery Voltage Monitoring Circuitry

Features

■ Supports coin-cell operated applications

■ 2.4 GHz Direct Sequence Spread Spectrum (DSSS) radio

transceiver

■ Operating voltage from 1.8 V to 3.6 V

■ Operating temperature from 0 to 70°C

■ Space saving 40-pin QFN 6x6 mm package

■ Operates in the unlicensed worldwide Industrial, Scientific,

and Medical (ISM) band (2.400 GHz to 2.483 GHz)

■ 21 mA operating current (Transmit at –5 dBm)

■ Transmit power up to +4 dBm

Applications

■ Wireless Keyboards and Mice

■ Wireless Gamepads

■ Remote Controls

■ Receive sensitivity up to –97 dBm

■ Sleep Current less than 1 μA

■ DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps

■ Low external component count

■ Toys

■ VOIP and Wireless Headsets

■ White Goods

■ Auto Transaction Sequencer (ATS) - no MCU intervention

■ Framing, Length, CRC16, and Auto ACK

■ Power Management Unit (PMU) for MCU/Sensor

■ Fast Startup and Fast Channel Changes

■ Separate 16-byte Transmit and Receive FIFOs

■ AutoRate™ - dynamic data rate reception

■ Receive Signal Strength Indication (RSSI)

■ Serial Peripheral Interface (SPI) control while in sleep mode

■ 4 MHz SPI microcontroller interface

■ Consumer Electronics

■ Home Automation

■ Automatic Meter Readers

■ Personal Health and Entertainment

Applications Support

See www.cypress.com for development tools, reference

designs, and application notes.

Logic Block Diagram

V_BAT

L/D

V_REG

V_DDV_CC

PACTL

Power Management

GFSK

Modulator

RF_P

RF_N

Data

DSSS

RF_BIAS

Interface

Baseband

and

IRQ

SS

SCK

MISO

MOSI

& Framer

Sequencer

SPI

GFSK

Demodulator

RSSI

Xtal Osc

Synthesizer

RST

XTAL XOUT

GND

Cypress Semiconductor Corporation

Document #: 38-16015 Rev. *J

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 18, 2011

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CYRF6936

Contents

Functional Description .....................................................3

Functional Overview ........................................................4

Data Transmission Modes ...........................................4

Link Layer Modes ........................................................4

Packet Buffers .............................................................5

Auto Transaction Sequencer (ATS) ............................5

Data Rates ..................................................................6

Functional Block Overview ..............................................6

2.4 GHz Radio .............................................................6

Frequency Synthesizer ................................................6

Baseband and Framer .................................................6

Packet Buffers and Radio Configuration Registers .....6

SPI Interface ................................................................6

Interrupts .....................................................................8

Clocks ..........................................................................8

Power Management ....................................................8

Low Noise Amplifier and Received

Application Examples ......................................................9

Registers .........................................................................14

Absolute Maximum Ratings ...........................................15

Operating Conditions .....................................................15

DC Characteristics ..........................................................15

AC Characteristics ..........................................................16

RF Characteristics ..........................................................17

Typical Operating Characteristics .................................19

Ordering Information ......................................................22

Ordering Code Definitions .........................................22

Package Description ......................................................23

Acronyms ........................................................................25

Document Conventions .................................................25

Units of Measure .......................................................25

Document History Page .................................................26

Sales, Solutions, and Legal Information ......................28

Worldwide Sales and Design Support .......................28

Products ....................................................................28

PSoC Solutions .........................................................28

Signal Strength Indication ............................................8

Receive Spurious Response .......................................9

Document #: 38-16015 Rev. *J

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CYRF6936

Functional Description

The CYRF6936 WirelessUSB™ LP radio is a second generation member of the Cypress WirelessUSB Radio System-On-Chip

(SoC) family. The CYRF6936 is interoperable with the first generation CYWUSB69xx devices. The CYRF6936 IC adds a range

of enhanced features, including increased operating voltage range, reduced supply current in all operating modes, higher data

rate options, reduced crystal start up, synthesizer settling, and link turnaround times.

Figure 1. Pin Diagram - CYRF6936 40 QFN

Corner

tabs

XTAL

NC

1

2

3

4

5

6

7

8

9

30 PACTL / GPIO

29 XOUT / GPIO

28 MISO / GPIO

27 MOSI / SDAT

26 IRQ / GPIO

25 SCK

V_CC

NC

CYRF6936

WirelessUSB LP

40-Pin QFN

NC

V_BAT1

V_CC

24 SS

V_BAT2

NC

23 NC

22 NC

* E-PAD Bottom Side

RF_BIAS10

21 NC

Table 1. Pin Description

Pin Number

Name

XTAL

Type

I

Default

Description

1

I

12 MHz crystal.

2, 4, 5, 9, 14, 15, 17, 18, NC

20, 21, 22, 23, 31, 32,

36, 39

NC

Connect to GND.

3, 7, 16

6, 8, 38

10

V_CC

Pwr

O

V_CC= 2.4 V to 3.6 V. Typically connected to V_REG.

V_BAT= 1.8 V to 3.6 V. Main supply.

V_BAT(0-2)

RF_BIAS

RF_P

O

I

RF I/O 1.8 V reference voltage.

11

I/O

GND

I/O

I

Differential RF signal to and from antenna.

Ground.

12

GND

RF_N

13

I

Differential RF signal to and from antenna.

Must be connected to GND.

19

RESV

SS

24

I

SPI enable, active LOW assertion. Enables and frames transfers.

SPI clock.

25

SCK

I

26

IRQ

I/O

O

I

Interrupt output (configurable active HIGH or LOW), or GPIO.

SPI data input pin (Master Out Slave In), or SDAT.

27

MOSI

MISO

28

Z

SPI data output pin (Master In Slave Out), or GPIO(in SPI 3-pin mode).

Tri-states when SPI 3PIN = 0 and SS is deasserted.

29

XOUT

I/O

O

Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.

Tri-states in sleep mode (configure as GPIO drive LOW).

30

33

PACTL

V_I/O

I/O

Control signal for external PA, T/R switch, or GPIO.

I/O interface voltage, 1.8–3.6 V.

Pwr

Document #: 38-16015 Rev. *J

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CYRF6936

Table 1. Pin Description (continued)

Pin Number

Name

RST

Type

Default

Description

34

I

Device reset. Internal 10 kohm pull down resistor. Active HIGH,

connect through a 0.47 μF capacitor to V_BAT.Must have RST = 1 event

the first time power is applied to the radio. Otherwise the state of the

radio control registers is unknown.

35

37

40

V_DD

L/D

Pwr

O

Decoupling pin for 1.8 V logic regulator, connect through a 0.47 μF

capacitor to GND.

PMU inductor/diode connection, when used. If not used, connect to

GND.

V_REG

GND

NC

Pwr

GND

NC

PMU boosted output voltage feedback.

Must be soldered to Ground.

E-PAD

Corner Tabs

Do Not solder the tabs and keep other signal traces clear. All tabs are

common to the lead frame or paddle which is grounded after the pad

is grounded. While they are visible to the user, they do not extend to

the bottom.

Data Transmission Modes

Functional Overview

The SoC supports four different data transmission modes:

The CYRF6936 IC provides a complete WirelessUSB SPI to

antenna wireless MODEMs. The SoC is designed to implement

wireless device links operating in the worldwide 2.4 GHz ISM

frequency band. It is intended for systems compliant with

worldwide regulations covered by ETSI EN 301 489-1 V1.41,

ETSI EN 300 328-1 V1.3.1 (Europe), FCC CFR 47 Part 15 (USA

and Industry Canada), and TELEC ARIB_T66_March, 2003

(Japan).

■ In GFSK mode, data is transmitted at 1 Mbps, without any

DSSS.

■ In 8DR mode, eight bits are encoded in each derived code

symbol transmitted.

■ In DDR mode, two bits are encoded in each derived code

symbol transmitted (As in the CYWUSB6934 DDR mode).

The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,

packet data buffering, packet framer, DSSS baseband controller,

Received Signal Strength Indication (RSSI), and SPI interface

for data transfer and device configuration.

■ In SDR mode, one bit is encoded in each derived code symbol

transmitted (As in the CYWUSB6934 standard modes).

Both 64 chip and 32 chip Pseudo Noise (PN) codes are

supported. The four data transmission modes apply to the data

after the SOP. In particular the length, data, and CRC16 are all

sent in the same mode. In general, lower data rates reduce

packet error rate in any given environment.

The radio supports 98 discrete 1 MHz channels (regulations may

limit the use of some of these channels in certain jurisdictions).

The baseband performs DSSS spreading/despreading, Start of

Packet (SOP), End of Packet (EOP) detection, and CRC16

generation and checking. The baseband may also be configured

to automatically transmit Acknowledge (ACK) handshake

packets whenever a valid packet is received.

Link Layer Modes

The CYRF6936 IC device supports the following data packet

framing features:

When in receive mode, with packet framing enabled, the device

is always ready to receive data transmitted at any of the

supported bit rates. This enables the implementation of

mixed-rate systems in which different devices use different data

rates. This also enables the implementation of dynamic data rate

systems that use high data rates at shorter distances or in a

low-moderate interference environment or both. It changes to

lower data rates at longer distances or in high interference

environments or both.

SOP

Packets begin with a two-symbol SoP marker. This is required in

GFSK and 8DR modes, but is optional in DDR mode and is not

supported in SDR mode. If framing is disabled then an SOP

event is inferred whenever two successive correlations are

detected. The SOP_CODE_ADR code used for the SOP is

different from that used for the “body” of the packet, and if desired

may be a different length. SOP must be configured to be the

same length on both sides of the link.

In addition, the CYRF6936 IC has a Power Management Unit

(PMU), which enables direct connection of the device to any

battery voltage in the range 1.8 V to 3.6 V. The PMU conditions

the battery voltage to provide the supply voltages required by the

device, and may supply external devices.

Length

There are two options for detecting the end of a packet. If SOP

is enabled, then the length field must be enabled. GFSK and

8DR must enable the length field. This is the first eight bits after

the SOP symbol, and is transmitted at the payload data rate.

When the length field is enabled, an EoP condition is inferred

after reception of the number of bytes defined in the length field,

plus two bytes for the CRC16. The alternative to using the length

Document #: 38-16015 Rev. *J

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CYRF6936

field is to infer an EOP condition from a configurable number of

successive noncorrelations; this option is not available in GFSK

mode and is only recommended when using SDR mode.

CRC16 detects the following errors:

■ Any one bit in error.

■ Any two bits in error (irrespective of how far apart, which

column, and so on).

CRC16

The device may be configured to append a 16 bit CRC16 to each

packet. The CRC16 uses the USB CRC polynomial with the

added programmability of the seed. If enabled, the receiver

verifies the calculated CRC16 for the payload data against the

received value in the CRC16 field. The seed value for the CRC16

calculation is configurable, and the CRC16 transmitted may be

calculated using either the loaded seed value or a zero seed; the

received data CRC16 is checked against both the configured

and zero CRC16 seeds.

■ Any odd number of bits in error (irrespective of the location).

■ An error burst as wide as the checksum itself.

Figure 2 shows an example packet with SOP, CRC16, and

lengths fields enabled, and Figure 3 shows a standard ACK

packet.

Figure 2. Example Packet Format

P ream ble

n x 16us

2nd Fram ing

S ym bol*

P

SO P 1

SO P 2

Length

C R C 16

Payload D ata

P acket

length

1 B yte

P eriod

1st Fram ing

S ym bol*

*N ote:32 or 64us

Figure 3. Example ACK Packet Format

P r e a m b le

1 6 u s

2 n d F r a m in g

S y m b o l*

n

x

P

S O P

1

S O P

2

C R C 1 6

C R C fie ld fr o m

r e c e iv e d p a c k e t.

1 s t F r a m in g

S y m b o l*

* N o te :3 2 o r 6 4 u s

2

B y te p e r io d s

Packet Buffers

Auto Transaction Sequencer (ATS)

All data transmission and reception use the 16 byte packet

buffers - one for transmission and one for reception.

The CYRF6936 IC provides automated support for transmission

and reception of acknowledged data packets.

The transmit buffer allows loading a complete packet of up to 16

bytes of payload data in one burst SPI transaction. This is then

transmitted with no further MCU intervention. Similarly, the

receive buffer allows receiving an entire packet of payload data

up to 16 bytes with no firmware intervention required until the

packet reception is complete.

When transmitting in transaction mode, the device automatically:

■ starts the crystal and synthesizer

■ enters transmit mode

■ transmits the packet in the transmit buffer

■ transitions to receive mode and waits for an ACK packet

The CYRF6936 IC supports packets up to 255 bytes. However,

the actual maximum packet length depends on the accuracy of

the clock on each end of the link and the data mode. Interrupts

are provided to allow an MCU to use the transmit and receive

buffers as FIFOs. When transmitting a packet longer than 16

bytes, the MCU can load 16 bytes initially, and add further bytes

to the transmit buffer as transmission of data creates space in

the buffer. Similarly, when receiving packets longer than 16

bytes, the MCU must fetch received data from the FIFO

periodically during packet reception to prevent it from

overflowing.

■ transitions to the transaction end state when an ACK packet is

received or a timeout period expires

Similarly, when receiving in transaction mode, the device

automatically:

■ waits in receive mode for a valid packet to be received

■ transitions to transmit mode, transmits an ACK packet

■ transitions to the transaction end state (receive mode to await

the next packet, and so on.)

The contents of the packet buffers are not affected by the

transmission or reception of ACK packets.

Document #: 38-16015 Rev. *J

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CYRF6936

In each case, the entire packet transaction takes place without

any need for MCU firmware action (as long as packets of 16

bytes or less are used). To transmit data, the MCU must load the

data packet to be transmitted, set the length, and set the TX GO

bit. Similarly, when receiving packets in transaction mode,

firmware must retrieve the fully received packet in response to

an interrupt request indicating reception of a packet.

Baseband and Framer

The baseband and framer blocks provide the DSSS encoding

and decoding, SOP generation and reception, CRC16

generation and checking, and EOP detection and length field.

Packet Buffers and Radio Configuration Registers

Packet data and configuration registers are accessed through

the SPI interface. All configuration registers are directly

addressed through the address field in the SPI packet (as in the

CYWUSB6934). Configuration registers allow configuration of

DSSS PN codes, data rate, operating mode, interrupt masks,

interrupt status, and so on.

Data Rates

The CYRF6936 IC supports the following data rates by

combining the PN code lengths and data transmission modes

described in the previous sections:

■ 1000 kbps (GFSK)

SPI Interface

■ 250 kbps (32 chip 8DR)

■ 125 kbps (64 chip 8DR)

■ 62.5 kbps (32 chip DDR)

■ 31.25 kbps (64 chip DDR)

■ 15.625 kbps (64 chip SDR)

The CYRF6936 IC has an SPI interface supporting

communication between an application MCU and one or more

slave devices (including the CYRF6936). The SPI interface

supports single-byte and multi-byte serial transfers using either

4-pin or 3-pin interfacing. The SPI communications interface

consists of Slave Select (SS), Serial Clock (SCK), Master

Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data

(SDAT).

Functional Block Overview

SPI communication may be described as the following:

2.4 GHz Radio

■ Command Direction (bit 7) = ‘1’ enables SPI write transaction.

A ‘0’ enables SPI read transactions.

The radio transceiver is a dual conversion low IF architecture

optimized for power, range, and robustness. The radio employs

channel-matched filters to achieve high performance in the

presence of interference. An integrated Power Amplifier (PA)

provides up to +4 dBm transmit power, with an output power

control range of 34 dB in seven steps. The supply current of the

device is reduced as the RF output power is reduced.

■ Command Increment (bit 6) = ‘1’ enables SPI auto address

increment. When set, the address field automatically

increments at the end of each data byte in a burst access.

Otherwise the same address is accessed.

■ Six bits of address

■ Eight bits of data

Table 2. Internal PA Output Power Step Table

The device receives SCK from an application MCU on the SCK

pin. Data from the application MCU is shifted in on the MOSI pin.

Data to the application MCU is shifted out on the MISO pin. The

active LOW Slave Select (SS) pin must be asserted to initiate an

SPI transfer.

PA Setting

Typical Output Power (dBm)

7

6

5

4

3

2

1

0

+4

0

–5

The application MCU can initiate SPI data transfers using a

multi-byte transaction. The first byte is the Command/Address

byte, and the following bytes are the data bytes shown in Table 3

through Figure 6 on page 7.

–13

–18

–24

–30

–35

The SPI communications interface has a burst mechanism,

where the first byte can be followed by as many data bytes as

required. A burst transaction is terminated by deasserting the

slave select (SS = 1).

The SPI communications interface single read and burst read

sequences are shown in Figure 4 and Figure 5 on page 7,

respectively.

Frequency Synthesizer

Before transmission or reception may begin, the frequency

synthesizer must settle. The settling time varies depending on

channel; 25 fast channels are provided with a maximum settling

time of 100 μs.

The SPI communications interface single write and burst write

sequences are shown in Figure 6 and Figure 7 on page 7,

respectively.

The ‘fast channels’ (less than 100 μs settling time) are every third

channel, starting at 0 up to and including 72 (for example, 0, 3,

6, 9 …. 69, 72).

This interface may be optionally operated in a 3-pin mode with

the MISO and MOSI functions combined in a single bidirectional

data pin (SDAT). When using 3-pin mode, user firmware must

ensure that the MOSI pin on the MCU is in a high impedance

state except when MOSI is actively transmitting data.

Document #: 38-16015 Rev. *J

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CYRF6936

The device registers may be written to or read from one byte at

a time, or several sequential register locations may be written or

read in a single SPI transaction using incrementing burst mode.

In addition to single byte configuration registers, the device

includes register files. Register files are FIFOs written to and

read from using nonincrementing burst SPI transactions.

The SPI interface is not dependent on the internal 12 MHz clock.

Registers may therefore be read from or written to when the

device is in sleep mode, and the 12 MHz oscillator disabled.

The SPI interface and the IRQ and RST pins have a separate

voltage reference pin (V_I/O). This enables the device to interface

directly to MCUs operating at voltages below the CYRF6936 IC

supply voltage.

The IRQ pin function may be optionally multiplexed onto the

MOSI pin. When this option is enabled, the IRQ function is not

available while the SS pin is LOW. When using this configuration,

user firmware must ensure that the MOSI pin on the MCU is in a

high impedance state whenever the SS pin is HIGH.

Table 3. SPI Transaction Format

Parameter

Bit #

Byte 1

Byte 1+N

[7:0]

7

6

[5:0]

Bit Name

DIR

INC

Address

Data

Figure 4. SPI Single Read Sequence

SCK

SS

cmd

addr

DIR

0

INC

A5

A4

A3

A2

A1

A0

MOSI

MISO

data to mcu

D7

D6

D5

D4

D3

D2

D1

D0

Figure 5. SPI Incrementing Burst Read Sequence

SCK

SS

cmd

addr

DIR

0

MOSI

MISO

INC

A5

A4

A3

A2

A1

A0

data to mcu₁

data to mcu_1+N

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

Figure 6. SPI Single Write Sequence

SCK

SS

cmd

addr

data from mcu

DIR

1

INC

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

MOSI

MISO

Figure 7. SPI Incrementing Burst Write Sequence

SCK

SS

cmd

addr

data from mcu₁

data from mcu_1+N

DIR

1

INC

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

MOSI

MISO

Document #: 38-16015 Rev. *J

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CYRF6936

The output voltage (V_REG) of the Power Management Unit

Interrupts

(PMU) is configurable to several minimum values between 2.4 V

and 2.7 V. V_REGmay be used to provide up to 15 mA (average

load) to external devices. It is possible to disable the PMU and

provide an externally regulated DC supply voltage to the device’s

main supply in the range 2.4 V to 3.6 V. The PMU also provides

a regulated 1.8 V supply to the logic.

The device provides an interrupt (IRQ) output, which is

configurable to indicate the occurrence of various different

events. The IRQ pin may be programmed to be either active

HIGH or active LOW, and be either a CMOS or open drain output.

The available interrupts are described in the section Registers

on page 14.

The PMU is designed to provide high boost efficiency (74–85%

depending on input voltage, output voltage, and load) when

using a Schottky diode and power inductor, eliminating the need

for an external boost converter in many systems where other

components require a boosted voltage. However, reasonable

efficiencies (69–82% depending on input voltage, output voltage,

and load) may be achieved when using low cost components

such as SOT23 diodes and 0805 inductors.

The CYRF6936 IC features three sets of interrupts: transmit,

receive, and system interrupts. These interrupts all share a

single pin (IRQ), but can be independently enabled or disabled.

The contents of the enable registers are preserved when

switching between transmit and receive modes.

If more than one interrupt is enabled at any time, it is necessary

to read the relevant status register to determine which event

caused the IRQ pin to assert. Even when a given interrupt source

is disabled, the status of the condition that would otherwise

cause an interrupt can be determined by reading the appropriate

status register. It is therefore possible to use the devices without

the IRQ pin, by polling the status registers to wait for an event,

rather than using the IRQ pin.

The current through the diode must stay within the linear

operating range of the diode. For some loads the SOT23 diode

is sufficient, but with higher loads it is not and an SS12 diode

must be used to stay within this linear range of operation. Along

with the diode, the inductor used must not saturate its core. In

higher loads, a lower resistance/higher saturation coil such as

the inductor from Sumida must be used.

Clocks

The PMU also provides a configurable low battery detection

function, which may be read over the SPI interface. One of seven

thresholds between 1.8 V and 2.7 V may be selected. The

interrupt pin may be configured to assert when the voltage on the

A 12 MHz crystal (30 ppm or better) is directly connected

between XTAL and GND without the need for external

capacitors. A digital clock out function is provided, with

selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This

output may be used to clock an external microcontroller (MCU)

or ASIC. This output is enabled by default, but may be disabled.

V_BATpin falls below the configured threshold. LV IRQ is not a

latched event. Battery monitoring is disabled when the device is

in sleep mode.

The requirements to directly connect the crystal to the XTAL pin

and GND are:

Low Noise Amplifier and Received Signal Strength

Indication

■ Nominal Frequency: 12 MHz

■ Operating Mode: Fundamental Mode

■ Resonance Mode: Parallel Resonant

■ Frequency Stability: ±30 ppm

■ Series Resistance: <60 ohms

■ Load Capacitance: 10 pF

The gain of the receiver can be controlled directly by clearing the

AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of

the RX_CFG_ADR register. Clearing the LNA bit reduces the

receiver gain approximately 20 dB, allowing accurate reception

of very strong received signals (for example, when operating a

receiver very close to the transmitter). Approximately 30 dB of

receiver attenuation can be added by setting the Attenuation

(ATT) bit. This limits data reception to devices at very short

ranges. Disabling AGC and enabling LNA is recommended,

unless receiving from a device using external PA.

■ Drive Level: 100 µW

When the device is in receive mode the RSSI_ADR register

returns the relative signal strength of the on-channel signal

power.

Power Management

The operating voltage of the device is 1.8 V to 3.6 V DC, which

is applied to the V_BATpin. The device can be shut down to a fully

static sleep mode by writing to the FRC END = 1 and

END STATE = 000 bits in the XACT_CFG_ADR register over the

SPI interface. The device enters sleep mode within 35 µs after

the last SCK positive edge at the end of this SPI transaction.

Alternatively, the device may be configured to automatically

enter sleep mode after completing the packet transmission or

reception. When in sleep mode, the on-chip oscillator is stopped,

but the SPI interface remains functional. The device wakes from

sleep mode automatically when the device is commanded to

enter transmit or receive mode. When resuming from sleep

mode, there is a short delay while the oscillator restarts. The

device can be configured to assert the IRQ pin when the

oscillator has stabilized.

When receiving, the device automatically measures and stores

the relative strength of the signal being received as a five bit

value. An RSSI reading is taken automatically when the SoP is

detected. In addition, a new RSSI reading is taken every time the

previous reading is read from the RSSI_ADR register, allowing

the background RF energy level on any given channel to be

easily measured when RSSI is read while no signal is being

received. A new reading can occur as fast as once every 12 µs.

Document #: 38-16015 Rev. *J

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CYRF6936

The workaround for this is to program an additional byte in the

packet header which contains the transmitter channel number.

After the packet is received, the channel number can be

checked. If the channel number does not match the receive

channel then the packet is rejected.

Receive Spurious Response

The transmitter may exhibit spurs around 50MHz offset at levels

approximately 50dB to 60dB below the carrier power. Receivers

operating at the transmit spur frequency may receive the spur if

the spur level power is greater than the receive sensitivity level.

Application Examples

Figure 8. Recommended Circuit for Systems where VBAT ≤ 2.4 V

2

1

0 4 0 2

V D D

0 4 0 2

3 5

0 4 0 2

V C C 3

V C C 2

V C C 1

1 6

7

3

0 4 0 2

E - P A D

4 1

0 4 0 2

V R E G

4 0

3 3

V I O

G N D 1

1 2

V B A T 0

V B A T 1

V B A T 2

3 8

6

8

V D D 1

V D D 2

V S S 1

2 4

5

2 7

V S S 2

4 4

Document #: 38-16015 Rev. *J

Page 9 of 28

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CYRF6936

Table 4. Recommended BoM for Systems where VBAT ≤ 2.4 V

Item Qty CY Part Number Reference Description

Manufacturer

NA

Mfr Part Number

1

NA

ANT1

2.5GHZ H-STUB WIGGLE

ANTENNA FOR 63MIL PCB

NA

2

3

1

NA

BH1

C1

BATTERY CLIPS 2AA CELL

730-10012

CAP 15PF 50 V CERAMIC NPO

0402

Panasonic

ECJ-0EC1H150J

4

5

1

730-11955

730-11398

C3

C4

CAP 2.0 PF 50 V CERAMIC NPO Kemet

0402

C0402C209C5GACTU

ECJ-0EC1H1R5C

CAP 1.5PF 50 V CERAMIC NPO PANASONIC

0402 SMD

6

7

2

730R-13322

730-13037

C5,C17

C12,C7

CAP CER .47UF 6.3 V X5R 0402 Murata

GRM155R60J474KE19D

C0805C106K9PACTU

CAP CERAMIC 10UF 6.3 V X5R

0805

Kemet

8

9

1

6

730-13400

730-13404

C8

CAP 1 uF 6.3 V CERAMIC X5R

0402

Panasonic

ECJ-0EB0J105M

0402YD473KAT2A

C9,C10,C11, CAP 0.047 uF 16 V CERAMIC X5R AVX

C13,C15,C16 0402

10

11

1

2

710-13201

730-10794

C18

CAP 100UF 10 V ELECT FC

Panasonic - ECG EEU-FC1A101S

Panasonic - ECG ECJ-0EB1C103K

C20,C19

CAP 10000PF 16 V CERAMIC

0402 SMD

12

1

800-13317

D1

DIODE SCHOTTKY 0.5A 40 V

SOT23

DIODES INC

BAT400D-7-F

13

14

1

NA

J1

J2

PCB COPPER PADS

NONE

420-11496

CONN HDR BRKWAY 5POS STR AMP Division of

AU PCB TYCO

103185-5

103185-1

15

16

17

1

420-11964

800-13401

800-11651

J3

L1

L2

HEADER 1 POS 0.230 HT MODII AMP/Tyco

.100CL

INDUCTOR 22NH 2% FIXED 0603 Panasonic - ECG ELJ-RE22NGF2

SMD

INDUCTOR 1.8NH +-.3NH FIXED Panasonic - ECG ELJ-RF1N8DF

0402 SMD

18

19

1

800-10594

630-11356

L3

COIL 10UH 1100MA CHOKE 0805 Newark

30K5421

R2

RES 1.00 OHM 1/8W 1% 0805

SMD

Yageo

9C08052A1R00FKHFT

20

21

1

610-13402

800-13368

R3

S1

RES47OHM1/16W5%0402SMD Panasonic - ECG ERJ-2GEJ470X

LT SWITCH 6MM 100GF H=7MM Panasonic - ECG EVQ-PAC07K

TH

22

23

1

CYRF6936-40LF U1

C

IC, LP 2.4 GHz RADIO SoC

QFN-40

Cypress

Semiconductor

CYRF6936 Rev A5

CY7C60123-PV U2

XC

IC WIRELESS EnCore II

CONTROLLER SSOP48

Cypress

Semiconductor

CY7C60123-PVXC

24

25

1

800-13259

Y1

CRYSTAL 12.00MHZ HC49 SMD eCERA

GF-1200008

PDC-9265-*B

PCB

PRINTED CIRCUIT BOARD

Cypress

Semiconductor

26

27

1

920-11206

LABEL1

LABEL2

Serial Number

PCA #

920-26504 *A

121-26504 *A

Document #: 38-16015 Rev. *J

Page 10 of 28

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CYRF6936

Table 4. Recommended BoM for Systems where VBAT ≤ 2.4 V (continued)

Item Qty CY Part Number Reference

Description

Manufacturer

Panasonic

Mfr Part Number

No Load Components - Do Not Install

28

29

30

31

32

1

730-13403

630-10242

730-13404

420-10921

620-10519

C6

R2

C7

J4

CAP 47UF 6.3 V CERAMIC X5R

1210

ECJ-4YB0J476M

RES CHIP 0.0 OHM 1/10W 5%

0805 SMD

Phycomp USA Inc 9C08052A0R00JLHFT

CAP 0.047 uF 50 V CERAMIC X5R AVX

0402

0402YD473KAT2A

644456-3

HEADER 3POS FRIC STRGHT

MTA 100

AMP/Tyco

R1

RES ZERO OHM 1/16W 5% 0603 Panasonic - ECG ERJ-3GEY0R00V

SMD

Document #: 38-16015 Rev. *J

Page 11 of 28

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CYRF6936

Figure 9. Recommended Circuit for Systems where V_BATis 2.4 V - 3.6 V (PMU Disabled)

2

1

0 4 0 2

V D D

3 5

V C C 3

1 6

V C C 2

7

V C C 1

3

P A E D -

4 1

V R E G

4 0

V I O

N D G 1

3 3

1 2

0

1

2

V B A T

3 8

6

8

0 4 0 2

V C C

V S S

8

1 1

0 4 0 2

Document #: 38-16015 Rev. *J

Page 12 of 28

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CYRF6936

Table 5. Recommended BoM for Systems where V_BATis 2.4 V - 3.6 V (PMU disabled)

Item Qty CY Part Number Reference

Description

Manufacturer

NA

Mfr Part Number

1

NA

ANT1

2.5GHZ H-STUB WIGGLE ANTENNA

FOR 32MIL PCB

NA

2

3

4

1

730-10012

730-11955

730-11398

C1

C3

C4

CAP 15PF 50 V CERAMIC NPO 0402

Panasonic

ECJ-0EC1H150J

CAP 2.0 PF 50 V CERAMIC NPO 0402 Kemet

C0402C209C5GACTU

ECJ-0EC1H1R5C

CAP 1.5PF 50 V CERAMIC NPO 0402 PANASONIC

SMD

5

6

7

1

6

730-13322

730-13404

C5, C15

CAP 0.47 uF 6.3 V CERAMIC X5R 0402 Murata

GRM155R60J474KE19D

0402YD473KAT2A

C6,C7,C8,C CAP 0.047 uF 16 V CERAMIC X5R 0402 AVX

9,C10,C11

8

1

730-11953

730-13040

730-12003

C12

C13

C14

CAP 1500PF 50 V CERAMIC X7R 0402 Kemet

CAP CERAMIC 4.7UF 6.3 V XR5 0805 Kemet

C0402C152K5RACTU

C0805C475K9PACTU

GRM21BR71A225KA01L

9

10

CAP CER 2.2UF 10 V 10% X7R 0805

Murata

Electronics North

America

11

12

13

14

1

800-13333

420-13046

800-13401

800-11651

D1

J1

L1

L2

LED GREEN/RED BICOLOR 1210 SMD LITEON

CONN USB PLUG TYPE A PCB SMT ACON

LTST-C155KGJRKT

UAR72-4N5J10

INDUCTOR 22NH 2% FIXED 0603 SMD Panasonic - ECG ELJ-RE22NGF2

INDUCTOR 1.8NH +-.3NH FIXED 0402 Panasonic - ECG ELJ-RF1N8DF

SMD

15

16

1

610-10343

610-13472

R1

R2

RES ZERO OHM 1/16W 0402 SMD

Panasonic - ECG ERJ-2GE0R00X

Panasonic - ECG ERJ-2GEJ621X

RES CHIP 620 OHM 1/16W 5% 0402

SMD

17

18

1

200-13471

S1

SWITCH LT 3.5MMX2.9MM 160GF SMD Panasonic - ECG EVQ-P7J01K

CYRF6936-40LFC U1

IC, LP 2.4 GHz RADIO SoC QFN-40

Cypress

Semiconductor

CYRF6936 Rev A5

19

1

CY7C63803-SXC U2

IC LOW SPEED USB ENCORE II

CONTROLLER SOIC16

Cypress

Semiconductor

CY7C63803-SXC

20

21

1

800-13259

Y1

CRYSTAL 12.00MHZ HC49 SMD

PRINTED CIRCUIT BOARD

eCERA

GF-1200008

PDC-9263-*B

PCB

Cypress

Semiconductor

22

23

1

LABEL1

LABEL2

Serial Number

PCA #

XXXXXX

121-26305 **

Document #: 38-16015 Rev. *J

Page 13 of 28

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CYRF6936

Registers

All registers are read and writable, except where noted. Registers may be written to or read from individually or in sequential groups.^{[1, 2]}

Table 6. Register Map Summary

Address

Mnemonic

b7

b6

b5

b4

b3

b2

b1

b0

Default^[1]Access^[1]

0x00

CHANNEL_ADR

Not Used

Channel

-1001000

00000000

00000011

-bbbbbbb

bbbbbbbb

0x01

0x02

0x03

0x04

TX_LENGTH_ADR

TX_CTRL_ADR

TX_CFG_ADR

TX Length

TXB15

IRQEN

TXB8

TXB0

IRQEN

TXBERR

IRQEN

TXC

TXE

TX GO

TX CLR

IRQEN

DATA CODE

LENGTH

--000101

--------

--bbbbbb

rrrrrrrr

Not Used

DATA MODE

PA SETTING

OS

IRQ

LV

IRQ

TXB15

IRQ

TXB8

IRQ

TXB0

IRQ

TXBERR

IRQ

TXC

IRQ

TXE

IRQ

TX_IRQ_STATUS_ADR

RX_CTRL_ADR

RX_CFG_ADR

RXB16

IRQEN

RXB8

IRQEN

RXB1

IRQEN

RXBERR

IRQEN

RXC

IRQEN

RXE

IRQEN

00000111

10010-10

--------

bbbbbbbb

bbbbb-bb

brrrrrrr

0x05

0x06

RX GO

RSVD

LNA

FAST

TURN EN

AGC EN

ATT

HILO

Not Used

RXOW EN

VLD EN

RXOW

IRQ

SOPDET

IRQ

RXB16

IRQ

RXB8

IRQ

RXB1

IRQ

RXBERR

IRQ

RXC

IRQ

RXE

IRQ

0x07

0x08

0x09

0x0A

RX_IRQ_STATUS_ADR

RX_STATUS_ADR

RX_COUNT_ADR

RX_LENGTH_ADR

PWR_CTRL_ADR

RX ACK

PKT ERR

EOP ERR

CRC0

Bad CRC

RX Code

RX Data Mode

--------

rrrrrrrr

RX Count

RX Length

PFET

00000000

10100000

rrrrrrrr

[1]

PMU EN

LVIRQ EN

IRQ POL

PMU Mode

Force

LVI TH

PMU OUTV

FREQ

bbbbbbbb

0x0B

[3]

disable

Not Used

XOUT OD PACTL OD

0x0C

0x0D

XTAL_CTRL_ADR

IO_CFG_ADR

XOUT FN

XSIRQ EN

MISO OD

Not Used

000--100

bbb--bbb

IRQ OD

PACTL

GPIO

SPI 3PIN

IRQ GPIO

00000000

bbbbbbbb

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

GPIO_CTRL_ADR

XACT_CFG_ADR

FRAMING_CFG_ADR

DATA32_THOLD_ADR

DATA64_THOLD_ADR

RSSI_ADR

XOUT OP

ACK EN

SOP EN

Not Used

SOP

MISO OP

Not Used

SOP LEN

Not Used

PACTL OP

FRC END

LEN EN

Not Used

LNA

IRQ OP

XOUT IP

MISO IP

PACTL IP

IRQ IP

0000----

1-000000

10100101

----0100

bbbbrrrr

b-bbbbbb

bbbbbbbb

----bbbb

---bbbbb

r-rrrrrr

END STATE

ACK TO

SOP TH

Not Used

TH32

TH64

RSSI

---01010

0-100000

10100100

[4]

HEN

HINT

EOP

bbbbbbbb

EOP_CTRL_ADR

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

CRC_SEED_LSB_ADR

CRC_SEED_MSB_ADR

TX_CRC_LSB_ADR

CRC SEED LSB

CRC SEED MSB

CRC LSB

00000000

--------

bbbbbbbb

rrrrrrrr

TX_CRC_MSB_ADR

RX_CRC_LSB_ADR

CRC MSB

--------

rrrrrrrr

CRC LSB

11111111

00000000

----0000

00000--0

0000000-

rrrrrrrr

RX_CRC_MSB_ADR

TX_OFFSET_LSB_ADR

TX_OFFSET_MSB_ADR

MODE_OVERRIDE_ADR

CRC MSB

rrrrrrrr

STRIM LSB

Not Used

bbbbbbbb

----bbbb

wwwww--w

bbbbbbb-

Not Used

RSVD

Not Used

RSVD

Not Used

FRC SEN

STRIM MSB

FRC AWAKE

FRC

Not Used

RST

0x1E

RX_OVERRIDE_ADR

ACK RX

RXTX DLY

MAN RXACK

RXDR

DIS CRC0 DIS RXCRC

ACE

Not Used

MAN

00000000

bbbbbbbb

0x1F

0x26

TX_OVERRIDE_ADR

XTAL_CFG_ADR

ACK TX

RSVD

FRC PRE

RSVD

TXACK

OVRD ACK DIS TXCRC

RSVD

RXF

TX INV

RSVD

START DLY

RSVD

00000000

00000011

00000000

wwwwwwww

0x27

CLK_OVERRIDE_ADR

CLK_EN_ADR

RSVD

0x28

RSVD

RXF

0x29

RX_ABORT_ADR

RSVD

ABORT EN

RSVD

0x32

AUTO_CAL_TIME_ADR

AUTO_CAL_OFFSET_ADR

ANALOG_CTRL_ADR

AUTO_CAL_TIME

0x35

AUTO_CAL_OFFSET

0x39

RSVD

RX INV

ALL SLOW

Register Files

0x20

TX_BUFFER_ADR

RX_BUFFER_ADR

SOP_CODE_ADR

DATA_CODE_ADR

PREAMBLE_ADR

MFG_ID_ADR

TX Buffer File

--------

Note 5

Note 6

Note 7

NA

wwwwwwww

rrrrrrrr

0x21

RX Buffer File

SOP Code File

Data Code File

Preamble File

MFG ID File

0x22

bbbbbbbb

rrrrrrrr

0x23

0x24

0x25

Notes

1. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined.

2. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode. The PMU, GPIOs, and RSSI registers can be accessed in Active Tx and

Rx mode.

3. PFET Bit: Setting this bit to "1" disables the FET, therefore safely allowing Vbat to be connected to a separate reference from Vcc when the PMU is disabled to the radio.

4. EOP_CTRL_ADR[6:4] must never have the value of “000”, that is, EOP Hint Symbol count must never be “0”

5. SOP_CODE_ADR default = 0x17FF9E213690C782.

6. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.

7. PREAMBLE_ADR default = 0x333302. The count value must be great than 4 for DDR and greater than 8 for SDR.

Document #: 38-16015 Rev. *J

Page 14 of 28

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CYRF6936

Static Discharge Voltage (Digital)^[9]..........................>2000 V

Static Discharge Voltage (RF)^[9]................................ 1100 V

Latch Up Current .....................................+200 mA, –200 mA

Absolute Maximum Ratings

Exceeding maximum ratings may shorten the useful life of the

device. User guidelines are not tested.

Storage Temperature.................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Operating Conditions

V_CC...................................................................2.4 V to 3.6 V

Supply Voltage on any power supply pin

relative to V_SS...............................................–0.3 V to +3.9 V

DC Voltage to Logic Inputs^[8].................–0.3 V to V_I/O+0.3 V

DC Voltage applied to Outputs

in High-Z State.......................................–0.3 V to V_I/O+0.3 V

V

_I/O...................................................................1.8 V to 3.6 V

V_BAT..................................................................1.8 V to 3.6 V

T_A(Ambient Temperature Under Bias)............. 0°C to +70°C

Ground Voltage................................................................. 0 V

F_OSC(Crystal Frequency)........................... 12 MHz ±30 ppm

DC Characteristics

(T = 25°C, V

= 2.4 V, PMU disabled, f

= 12.000000 MHz)

BAT

OSC

Parameter

Description

Battery Voltage

Conditions

Min

1.8

2.4

2.7

1.8

Typ

Max

Unit

V

0–70°C

3.6

BAT

[10]

PMU Output Voltage

2.4 V mode

2.7 V mode

2.43

2.73

V

REG

V

REG

[11]

V

Voltage

3.6

V

I/O

CC

OH1

OH2

OL

IH

I/O

CC

[12]

0–70°C

2.4

V

Output High Voltage Condition 1

Output High Voltage Condition 2

Output Low Voltage

At I = –100.0 µA

V

– 0.2

– 0.4

V

OH

I/O

At I = –2.0 mA

V

OH

At I = 2.0 mA

0

0.45

V

OL

Input High Voltage

0.7 V

0

V

I/O

Input Low Voltage

0.3 V

+1

V

IL

I/O

I

Input Leakage Current

Pin Input Capacitance

0 < V < V

I/O

–1

0.26

3.5

µA

pF

mA

µA

mA

%

IL

IN

C

except XTAL, RF , RF , RF

BIAS

10

IN

CC

N

P

[13]

I

(GFSK)

Average TX I , 1 Mbps, slow channel PA = 5, 2 way, 4 bytes/10 ms

0.87

1.2

CC

[13]

(32-8DR)

Average TX I , 250 kbps, fast channel PA = 5, 2 way, 4 bytes/10 ms

CC

[14]

Sleep Mode I

0.8

10

SB

CC

[14]

PMU enabled

31.4

1.0

IDLE I

Radio off, XTAL Active

XOUT disabled

CC

I

during Synth Start

during Transmit

during Receive

8.4

synth

CC

TX I

PA = 5 (–5 dBm)

PA = 6 (0 dBm)

PA = 7 (+4 dBm)

LNA off, ATT on

LNA on, ATT off

20.8

26.2

34.1

18.4

21.2

81

CC

RX I

CC

Boost Eff

PMU Boost Converter Efficiency

Average PMU External Load current

V

= 2.5 V, V

= 20 mA

= 2.73 V,

BAT

REG

I

LOAD

[15]

I

V

= 1.8 V, V

BAT

= 2.73 V,

15

10

mA

LOAD_EXT

REG

0–50°C, RX Mode

V

= 1.8 V, V

= 2.73 V, 50–70°C, RX

REG

BAT

Mode

Notes

8. It is permissible to connect voltages above V to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed.

I/O

9. Human Body Model (HBM).

10. V

depends on battery input voltage.

REG

11. In sleep mode, the I/O interface voltage reference is V

.

BAT

12. In sleep mode, V min. can be as low as 1.8 V.

CC

13. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK

handshake. Device is in sleep except during this transaction.

14. ISB is not guaranteed if any I/O pin is connected to voltages higher than V

.

I/O

15. I

is dependent on external components and this entry applies when the components connected to L/D are SS12 series diode and DH53100LC inductor from

LOAD_EXT

Sumida.

Document #: 38-16015 Rev. *J

Page 15 of 28

[+] Feedback

CYRF6936

AC Characteristics^[16]

Table 7. SPI Interface^[17]

Parameter

Description

Min

238.1

100

25

Typ

Max

Unit

ns

t_{SCK_CYC}

t_{SCK_HI}

SPI Clock Period

SPI Clock High Time

t_{SCK_LO}

t_{DAT_SU}

t_{DAT_HLD}

t_{DAT_VAL}

t_{DAT_VAL_TRI}

t_{SS_SU}

SPI Clock Low Time

SPI Input Data Setup Time

SPI Input Data Hold Time

SPI Output Data Valid Time

10

0

50

20

SPI Output Data Tri-state (MOSI from Slave Select Deassert)

SPI Slave Select Setup Time before first positive edge of SCK^[18]

SPI Slave Select Hold Time after last negative edge of SCK

SPI Slave Select Minimum Pulse Width

10

20

10

t_{SS_HLD}

t_{SS_PW}

t_{SCK_SU}

t_{SCK_HLD}

t_RESET

SPI Slave Select Setup Time

SPI SCK Hold Time

Minimum RST Pin Pulse Width

Figure 10. SPI Timing

t_{SCK_CYC}

t_{SCK_HI}

t_{SCK_LO}

SCK

nSS

t_{SCK_HLD}

t_{SCK_SU}

t_{SS_SU}

t_{SS_HLD}

t_{DAT_SU}

t_{DAT_HLD}

MOSI input

MISO

t_{DAT_VAL}

t_{DAT_VAL_TRI}

MOSI output

Notes

16. AC values are not guaranteed if voltage on any pin exceeding V

.

I/O

17. C

= 30 pF

LOAD

18. SCK must start low at the time SS goes LOW, otherwise the success of SPI transactions are not guaranteed.

Document #: 38-16015 Rev. *J

Page 16 of 28

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CYRF6936

RF Characteristics

Table 8. Radio Parameters

Parameter Description

Conditions

Min

Typ

Max

Unit

RF Frequency Range

Note 19

= 12.000000 MHz, BER < 1E-3)

BER 1E-3

2.400

2.497

GHz

Receiver (T = 25°C, V = V

= 3.0 V, f

OSC

CC

BAT

Sensitivity 125 kbps 64-8DR

Sensitivity 250 kbps 32-8DR

Sensitivity

–97

–93

–87

–84

22.8

–31.7

–6

dBm

BER 1E-3

CER 1E-3

–80

–15

dBm

Sensitivity GFSK

LNA Gain

BER 1E-3, ALL SLOW = 1

dBm

dB

ATT Gain

dB

Maximum Received Signal

RSSI Value for PWR_in–60 dBm^[20]

LNA On

dBm

21

Count

dB/Count

RSSI Slope

1.9

Interference Performance (CER 1E-3)

Co-channel Interference rejection

Carrier-to-Interference (C/I)

C = –60 dBm

9

dB

Adjacent (±1 MHz) channel selectivity C/I 1 MHz

Adjacent (±2 MHz) channel selectivity C/I 2 MHz

Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz

Out-of-Band Blocking 30 MHz–12.75 MHz^[21]

Intermodulation

C = –60 dBm

3

dB

C = –60 dBm

–30

–38

–30

–36

C = –67 dBm

dB

C = –67 dBm

dBm

C = –64 dBm, Δf = 5,10 MHz

Receive Spurious Emission

800 MHz

100 kHz ResBW

–79

–71

–65

dBm

1.6 GHz

3.2 GHz

Transmitter (T = 25°C, V = 3.0 V)

CC

Maximum RF Transmit Power

RF Power Control Range

PA = 7

PA = 6

PA = 5

PA = 0

+2

–2

–7

4

+6

+2

–3

dBm

dB

0

–5

–35

39

RF Power Range Control Step Size

Frequency Deviation Min

Seven steps, monotonic

PN Code Pattern 10101010

PN Code Pattern 11110000

>0 dBm

5.6

270

323

10

dB

kHz

%rms

kHz

Frequency Deviation Max

Error Vector Magnitude (FSK error)

Occupied Bandwidth

–6 dBc, 100 kHz ResBW

500

876

Transmit Spurious Emission (PA = 7)

In-band Spurious Second Channel Power (±2 MHz)

In-band Spurious Third Channel Power (>3 MHz)

–38

–44

dBm

Notes

19. Subject to regulation.

20. RSSI value is not guaranteed. Extensive variation from part to part.

21. Exceptions F/3 & 5C/3.

Document #: 38-16015 Rev. *J

Page 17 of 28

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CYRF6936

Table 8. Radio Parameters (continued)

Parameter Description

Non-Harmonically Related Spurs (800 MHz)

Non-Harmonically Related Spurs (1.6 GHz)

Non-Harmonically Related Spurs (3.2 GHz)

Harmonic Spurs (Second Harmonic)

Harmonic Spurs (Third Harmonic)

Fourth and Greater Harmonics

Power Management (Crystal PN# eCERA GF-1200008)

Crystal Start to 10ppm

Conditions

Min

Typ

–38

–34

–47

–43

–48

–59

Max

Unit

dBm

0.7

0.6

1.3

ms

µs

Crystal Start to IRQ

XSIRQ EN = 1

Synth Settle

Slow channels

Medium channels

Fast channels

GFSK

270

180

100

30

Synth Settle

µs

Synth Settle

µs

Link Turnaround Time

µs

Link Turnaround Time

250 kbps

62

µs

Link Turnaround Time

125 kbps

94

µs

Link Turnaround Time

<125 kbps

31

µs

Max Packet Length

<60 ppm crystal-to-crystal

all modes except 64-DDR and

64-SDR

40

bytes

Max Packet Length

<60 ppm crystal-to-crystal

64-DDR and 64-SDR

16

bytes

Document #: 38-16015 Rev. *J

Page 18 of 28

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CYRF6936

Typical Operating Characteristics^[22]

Transmit Power vs. Temperature

Transmit Power vs. Vcc

(PMU off)

Transmit Power vs. Channel

(Vcc

=

2.7v)

6

4

PA7

PA6

6

4

6

4

PA7

PA6

PA7

PA6

2

0

-2

-4

-6

-8

-10

-12

-14

-2

-4

-6

-8

-10

-12

-14

-2

-4

-6

-8

-10

-12

-14

PA5

PA4

PA5

PA4

PA5

PA4

0

20

40

Temp (deg C)

60

2.4

2.6

2.8

3

3.2

3.4

3.6

0

20

40

60

80

Vcc

Channel

Typical RSSI Count vs Input Power

Average RSSI vs. Temperature

(Rx signal -70dBm)

Average RSSI vs. Vcc

(Rx signal -70dBm)

=

32

20

19

18

17

16

15

14

13

12

11

10

19

18

17

16

15

14

13

12

24

16

8

LNA ON

LNA OFF

ATT ON

LNA OFF

0

2.4

2.6

2.8

3

3.2

3.4

3.6

0

20

40

60

-120

-100

-80

-60

-40

-20

Vcc

Temp (deg C)

Input Power (dBm)

RSSI vs. Channel

Rx Sensitivity vs. Vcc

(1Mbps CER)

Rx Sensitivity vs. Temperature

(1Mbps CER)

(Rx signal

= -70dBm)

18

16

14

12

10

8

-80

-82

-84

-86

-88

-90

-92

-94

-80

-82

-84

-86

-88

-90

-92

-94

CER

6

4

8DR32

2

0

20

40

Channel

60

80

2.4

2.6

2.8

3

3.2

3.4

3.6

0

20

40

60

Vcc

Temp (deg C)

Receiver Sensitivity vs. Frequency Offset

Receiver Sensitivity vs Channel

(3.0v, Room Temp)

Carrier to Interferer

(Narrow band, LP modulation)

-80

-81

-83

-85

-87

-89

-91

-93

-95

20.0

10.0

-82

-84

-86

-88

-90

-92

-94

-96

-98

GFSK

CER

0.0

GFSK

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

DDR32

8DR64

DDR32

8DR32

-150

-100

-50

0

50

100

150

-10

-5

0

5

10

0

20

40

60

80

Crystal Offset (ppm)

Channel Offset (MHz)

Channel

Note

22. With LNA on, ATT off, above -2dBm erroneous RSSI values may be read. Cross-checking RSSI with LNA off/on is recommended for accurate readings.

Document #: 38-16015 Rev. *J

Page 19 of 28

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CYRF6936

Typical Operating Characteristics (continued)

GFSK vs. BER

BER vs. Data Threshold (32-DDR)

BER vs. Data Threshold (32-8DR)

(SOP Threshold 5, C38 slow)

(SOP Threshold

=

5, C38 slow)

(SOP Threshold

=

5, C38 slow)

=

100

10

1

10

1

0

Thru 7

3

1

0

6

1

0.1

0.01

0.001

0.0001

0.00001

0.001

0.0001

0.00001

0.001

0.0001

0.00001

GFSK

-100

-80

-60

-40

-20

0

-100

-95

-90

-85

-80

-75

-70

-100

-95

-90

-85

-80

-75

-70

Input Power (dBm)

ICC RX

ICC RX SYNTH

ICC RX

(LNA OFF)

(LNA ON)

9.2

25

24.5

24

21

20.5

20

9.1

9

3.3

V

3.3

3.0

2.7

2.4

V

3.3

3.0

2.7

2.4

V

3.0

2.7

2.4

V

8.9

8.8

8.7

8.6

8.5

8.4

8.3

8.2

8.1

8

V

23.5

23

V

19.5

19

22.5

22

21.5

21

18.5

18

20.5

20

17.5

17

19.5

19

7.9

7.8

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

ICC TX

@

PA1

ICC TX SYNTH

ICC TX @ PA0

9.2

9.1

9

17

17.5

17

3.3

3.0

2.7

2.4

V

3.3

3.0

2.7

2.4

V

3.3

V

16.5

16

V

3.0

2.7

2.4

V

8.9

8.8

8.7

8.6

8.5

8.4

8.3

8.2

8.1

8

V

16.5

16

15.5

15

15.5

15

14.5

14

14.5

14

7.9

7.8

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

ICC TX

@

PA4

ICC TX

@

PA2

ICC TX

@

PA3

20.5

20

18

17.5

17

19

3.3

3.0

2.7

2.4

V

3.3

3.0

2.7

2.4

V

18.5

18

3.3

3.0

2.7

2.4

V

19.5

19

V

17.5

17

18.5

18

16.5

16

16.5

16

17.5

17

15.5

15

15.5

16.5

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

Document #: 38-16015 Rev. *J

Page 20 of 28

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CYRF6936

Typical Operating Characteristics (continued)

ICC TX

@ PA7

ICC TX

@

PA5

ICC TX @ PA6

40.5

40

30

29.5

29

23.5

23

3.3

V

39.5

39

3.3

V

3.3

V

3.0

2.7

2.4

V

3.0

2.7

2.4

V

3.0

2.7

2.4

V

38.5

38

V

22.5

22

28.5

28

V

37.5

37

27.5

27

36.5

36

21.5

21

35.5

35

26.5

26

34.5

34

20.5

20

25.5

25

33.5

33

32.5

19.5

24.5

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70

TEMPERATURE (C)

Figure 11. AC Test Loads and Waveforms for Digital Pins

AC Test Loads

OUTPUT

DC Test Load

OUTPUT

R1

V

CC

5 pF

30 pF

OUTPUT

INCLUDING

JIG AND

SCOPE

INCLUDING

JIG AND

SCOPE

R2

Max

Typical

ALL INPUT PULSES

V

Parameter

R1

Unit

Ω

V

CC

90%

10%

90%

10%

1071

937

500

1.4

GND

R2

Fall time: 1 V/ns

R_TH

Rise time: 1 V/ns

V_TH

THÉVENIN EQUIVALENT

Equivalent to:

OUTPUT

V_CC

3.00

V

R

TH

V

TH

Document #: 38-16015 Rev. *J

Page 21 of 28

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CYRF6936

Ordering Information

Part Number

Radio

Package Name

40-Pin QFN

Package Type

40-Pin Quad Flat Package Pb-free

40-Pin QFN (Sawn type)

Operating Range

CYRF6936-40LFXC

CYRF6936-40LTXC

Transceiver

Commercial

40-Pin QFN

Ordering Code Definitions

C

6936

CYRF

40L(F,T)X

Temperature range:

Commercial

40-pin package

F = QFN; T = Sawn QFN

X = Pb-free

Part Number

Marketing Code: RF = Wireless

(radio frequency) product line

Company ID: CY = Cypress

Document #: 38-16015 Rev. *J

Page 22 of 28

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CYRF6936

Package Description

Figure 12. 40-Pin Pb-free QFN 6 × 6 mm

SOLDERABLE

EXPOSED

PAD

001-12917 *C

The recommended dimension of the PCB pad size for the E-PAD underneath the QFN is 3.5 mm × 3.5 mm (width × length).

Document #: 38-16015 Rev. *J

Page 23 of 28

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CYRF6936

Figure 13. 40-Pin Sawn QFN (6 × 6 × 0.90 mm)

001-44328 *D

Document #: 38-16015 Rev. *J

Page 24 of 28

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CYRF6936

Acronyms

Document Conventions

Table 9. Acronyms Used in this Document

Units of Measure

Acronym

ACK

Description

Acknowledge (packet received, no errors)

Bit error rate

Table 10. Units of Measure

Symbol

Unit of Measure

BER

BOM

CMOS

CRC

GFSK

HBM

ISM

°C

degree Celsius

decibels

Bill of materials

dB

Complementary metal oxide semiconductor

Cyclic redundancy check

Gaussian frequency-shift keying

Human body model

dBc

dBm

Hz

decibel relative to carrier

decibel-milliwatt

hertz

KB

1024 bytes

1024 bits

Kbit

kHz

kΩ

Industrial, scientific, and medical

Interrupt request

kilohertz

IRQ

kilohm

MCU

QFN

RSSI

RF

Microcontroller unit

MHz

MΩ

μA

megahertz

megaohm

Quad flat no-leads

Received signal strength indication

Radio frequency

microampere

microsecond

microvolts

μs

Rx

Receive

μV

Tx

Transmit

μVrms

μW

mA

ms

mV

nA

microvolts root-mean-square

microwatts

milliampere

millisecond

millivolts

nanoampere

nanosecond

nanovolts

ns

nV

Ω

ohm

pp

peak-to-peak

parts per million

picosecond

volts

ppm

ps

V

Document #: 38-16015 Rev. *J

Page 25 of 28

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CYRF6936

Document History Page

Description Title: CYRF6936 WirelessUSB™ LP 2.4 GHz Radio SoC

Document Number: 38-16015

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

**

307437

377574

TGE

See ECN

New data sheet

Preliminary release–

*A

- updated Section 1.0 - Features

- updated Section 2.0 - Applications

- added Section 3.0 - Applications Support

- updated Section 4.0 - Functional Descriptions

- updated Section 5.0 - Pin Description

- added Figure 5-1

- updated Section 6.0 - Functional Overview

- added Section 7.0 - Functional Block Overview

- added Section 9.0 - Register Descriptions

- updated Section 10.0 - Absolute Maximum Ratings

- updated Section 11.0 - Operating Conditions

- updated Section 12.0 - DC Characteristics

- updated Section 13.0 - AC Characteristics

- updated Section 14.0 - RF Characteristics

- added Section 16.0 - Ordering Information

*B

*C

398756

412778

TGE

See ECN

ES-10 update-

- changed part no.

- updated Section 9.0 - Register Descriptions

- updated Section 12.0 - DC Characteristics

- updated Section 14.0 - RF Characteristics

ES-10 update-

- updated Section 4.0 - Functional Descriptions

- updated Section 5.0 - Pin Descriptions

- updated Section 6.0 - Functional Overview

- updated Section 7.0 - Functional Block Overview

- updated Section 9.0 - Register Descriptions

- updated Section 10.0 - Absolute Maximum Ratings

- updated Section 11.0 - Operating Conditions

- updated Section 14.0 - RF Characteristics

*D

435578

TGE

See ECN

- updated Section 1.0 - Features

- updated Section 5.0 - Pin Descriptions

- updated Section 6.0 - Functional Overview

- updated Section 7.0 - Functional Block Overview

- updated Section 9.0 - Register Descriptions

- added Section 10.0 - Recommended Radio Circuit Schematic

- updated Section 11.0 - Absolute Maximum Ratings

- updated Section 12.0 - Operating Conditions

- updated Section 13.0 - DC Characteristics

- updated Section 14.0 - AC Characteristics

- updated Section 15.0 - RF Characteristics

*E

*F

460458

487261

BOO

TGE

See ECN

Final data sheet - removed “Preliminary” notation

- updated Section 1.0 - Features

- updated Section 5.0 - Pin Descriptions

- updated Section 6.0 - Functional Overview

- updated Section 7.0 - Functional Block Overview

- updated Section 8.0 - Application Example

- updated Section 9.0 - Register Descriptions

- updated Section 12.0 - DC Characteristics

- updated Section 13.0 - AC Characteristics

- updated Section 14.0 - RF Characteristics

- added Section 15.0 - Typical Operating Characteristics

Document #: 38-16015 Rev. *J

Page 26 of 28

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CYRF6936

Document History Page (continued)

Description Title: CYRF6936 WirelessUSB™ LP 2.4 GHz Radio SoC

Document Number: 38-16015

Orig. of

Change

Submission

Date

Revision

ECN

Description of Change

*G

778236

OYR/ARI

See ECN

-modified radio function register descriptions

-changed L/D pin description

-footnotes added

-changed RST Capacitor from 0.1uF to 0.47 uF

-updated Figure 9, Recommended Circuit for Systems

-updated Table 3, Recommended bill of materials for systems

-updated package diagram from ** to *A

*H

2640987 VNY/OYR/TGE/

AESA

02/20/2009

-Removed range values in features description

-Bit level register details removed and appended to the Wireless LP and

PRoC TRM

-updated register summary table 4

-updated pin description diagram (figure 1)

-updated the schematic of the radio (figure 10).

-Removed Backward Compatibility section.

-Removed Table 2

-Updated RF table characteristics for Payload size

-Added pkg diagram 001-12917

-Updated BOM Table 4 on page 10.

-Updated Table 8 on page 17 with Receiver information (T = 25°C,

V_CC= V_BAT= 3.0 V, f_OSC= 12.000000 MHz, BER < 1E-3)

*I

2673333

3232571

TGE/PYRS

JCJC

03/13/2009

04/18/2011

Corrected Figure 9 on page 12

Updated packaging and ordering information for 40 QFN (sawn)

package

*J

Added section Receive Spurious Response on page 9.

Added note # 20 and referred in Table 8 on page 17.

Updated template as per new Cypress standards.

Added ordering code definitions, acronyms, and units of measure.

Updated package diagrams:

001-12917: *A to *C

001-44328: *C to *D

Document #: 38-16015 Rev. *J

Page 27 of 28

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CYRF6936

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

PSoC Solutions

Clocks & Buffers

Interface

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/image

cypress.com/go/psoc

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-16015 Rev. *J

Revised April 18, 2011

Page 28 of 28

All products and company names mentioned in this document may be the trademarks of their respective holders.

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厂商	型号	描述	页数
KYOCERA AVX	CYR10	玻璃电容器CYR10 ， 15 （可靠性指标） M23269 / 01 ， 02 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR10, 15 (Established Reliability) M23269/01, 02 (QPL to MIL-PRF-23269) ]	2 页
FOXCONN	CYR2-AP03MJ04	[ Interconnection Device ]	1 页
KYOCERA AVX	CYR51	玻璃电容器CYR51 ， 52 ， 53 （可靠性指标） M23269 / 10 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR51, 52, 53 (Established Reliability) M23269/10 (QPL to MIL-PRF-23269) ]	2 页
KYOCERA AVX	CYR52	玻璃电容器CYR51 ， 52 ， 53 （可靠性指标） M23269 / 10 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR51, 52, 53 (Established Reliability) M23269/10 (QPL to MIL-PRF-23269) ]	2 页
KYOCERA AVX	CYR53	玻璃电容器CYR51 ， 52 ， 53 （可靠性指标） M23269 / 10 （ QPL至MIL-PRF- 23269 ）[ Glass Capacitors CYR51, 52, 53 (Established Reliability) M23269/10 (QPL to MIL-PRF-23269) ]	2 页
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CYPRESS	CYRF69103-40LFXC	无线可编程片上低功耗的16位自由运行定时器[ Programmable Radio on Chip Low Power 16-bit free running timer ]	68 页
CYPRESS	CYRF69103-40LTXC	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	72 页
CYPRESS	CYRF69103A-40LFXC	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	68 页
CYPRESS	CYRF69103_08	无线可编程片上低功耗[ Programmable Radio on Chip Low Power ]	65 页